Physical Design Engineer, FullChip/ASIC Implementation

Socket.dev; Mountain View (CA); On-site; USD 118,000 - 197,000; Full time

Job summary

Google is seeking a Senior ASIC Engineer in Mountain View to lead the RTL2GDS flow for high-performance, power-efficient ASICs. You will drive full-chip physical implementation and partner with cross-functional teams to deliver cutting-edge silicon solutions.

Ideal candidates have a strong background in physical design, high-performance PnR, STA optimizations, and a deep understanding of ASIC design flows. Join a team shaping the future of hardware experiences at Google.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience in physical design.
• Experience with synthesis/PNR tools such as Genus, Innovus, DC, ICC.
• Understanding of high-performance synthesis, PnR, sign-off convergence and STA optimizations.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
• Manage full-chip level physical implementation.
• Define and implement innovative schemes to improve performance and power.
• Work with cross-functional teams to deliver best quality of results.

Skills

Physical design experience

Synthesis/PNR tools

STA & sign-off optimization

ASIC design flow understanding

Education

Bachelor's degree in Electrical Engineering or equivalent practical experience

Tools

Genus

Innovus

DC

ICC

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience in physical design.
• Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
• Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.

Preferred qualifications:

• Experience in top-level floorplanning and block integration.
• Experience in low power design implementation including UPF/CPF, multi-voltage domains and power gating.
• Experience with ASIC design flows and methodology of physical design.
• Understanding of circuit design, device physics, and deep submicron technology.
• Knowledge of Verilog/SystemVerilog and fundamentals of computer architecture.
• Effective skills with scripting languages such as Tcl, or Perl.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
• Manage full-chip level physical implementation.
• Define and implement innovative schemes to improve performance and power.
• Work with cross-functional teams to deliver best quality of results.