Senior ASIC Physical Design Eng - Full-Chip PPA, Equity

Socket.dev; Mountain View (CA); On-site; USD 118,000 - 197,000; Full time

Job summary

Google is seeking a Senior ASIC Engineer in Mountain View to lead the RTL2GDS flow for high-performance, power-efficient ASICs. You will drive full-chip physical implementation and partner with cross-functional teams to deliver cutting-edge silicon solutions.

Ideal candidates have a strong background in physical design, high-performance PnR, STA optimizations, and a deep understanding of ASIC design flows. Join a team shaping the future of hardware experiences at Google.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience in physical design.
• Experience with synthesis/PNR tools such as Genus, Innovus, DC, ICC.
• Understanding of high-performance synthesis, PnR, sign-off convergence and STA optimizations.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
• Manage full-chip level physical implementation.
• Define and implement innovative schemes to improve performance and power.
• Work with cross-functional teams to deliver best quality of results.

Skills

Physical design experience

Synthesis/PNR tools

STA & sign-off optimization

ASIC design flow understanding

Education

Bachelor's degree in Electrical Engineering or equivalent practical experience

Tools

Genus

Innovus

DC

ICC

Job description

Google is seeking a Senior ASIC Engineer in Mountain View to lead the RTL2GDS flow for high-performance, power-efficient ASICs. You will drive full-chip physical implementation and partner with cross-functional teams to deliver cutting-edge silicon solutions.

Ideal candidates have a strong background in physical design, high-performance PnR, STA optimizations, and a deep understanding of ASIC design flows. Join a team shaping the future of hardware experiences at Google.