ASIC Physical Design Engineer — Full-Chip Implementation

Google; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is hiring for a lead Physical Designer to drive all aspects of ASIC RTL2GDS implementation and full-chip physical design. You will work on high-performance, power-efficient hardware that powers Google's products, collaborating across design, verification, and infrastructure teams.

The role requires a degree in Electrical Engineering or equivalent, 4+ years in physical design, and hands-on experience with synthesis and PnR tools, STA, and sign-off optimization.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience in physical design.
• Experience in synthesis, place-and-route (PnR) and sign-off convergence including STA and sign-off optimizations.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
• Manage full-chip level physical implementation.
• Define and implement innovative schemes to improve performance and power.
• Work with cross-functional teams to deliver best quality of results.

Skills

Top-level floorplanning

Block integration

Circuit design fundamentals

Verilog/SystemVerilog

Scripting languages (Tcl/Perl)

Education

Bachelor's degree in Electrical Engineering or equivalent practical experience

Tools

Genus

Innovus

DC

ICC

Job description

Google is hiring for a lead Physical Designer to drive all aspects of ASIC RTL2GDS implementation and full-chip physical design. You will work on high-performance, power-efficient hardware that powers Google's products, collaborating across design, verification, and infrastructure teams.

The role requires a degree in Electrical Engineering or equivalent, 4+ years in physical design, and hands-on experience with synthesis and PnR tools, STA, and sign-off optimization.