Senior ASIC Physical Design Engineer — Equity, Cambridge

Alpaca Research; Cambridge (MA); On-site; USD 300,000 - 350,000; Full time

Job summary

Alpaca Research in Cambridge, MA seeks a Staff Physical Design Engineer to own ASIC implementation from floorplanning to tapeout. This on-site role requires leading full-chip timing, power, and signoff, mentoring the team and coordinating with foundry and backend partners.

The candidate will drive RTL-to-GDSII flow, macro placement, clock distribution, power integrity, and physical verification for advanced nodes, using Cadence or Synopsys toolchains. Excellent communication is essential.

Qualifications

• 8+ years of hands-on ASIC physical design experience.
• Multiple tapeouts with top-level physical signoff responsibility.
• Experience at 16 nm or smaller FinFET nodes.
• Proficiency in RTL-to-GDSII flow with Cadence or Synopsys toolchains.
• Strong Tcl and Python scripting for flows.
• Clear communication of implementation results to architects and leadership.

Responsibilities

• Own full-chip floorplan and partitioning, SRAM macro placement, I/O and bump planning with the package team.
• Set area, timing and power budgets for each partition.
• Lead top-level implementation: clock distribution, power-grid design, and integration of blocks and hard IP.
• Own chip-level timing constraints and signoff across modes and corners, including ECOs.
• Define and maintain reproducible implementation methodology for the team.
• Mentor physical-design engineers and review implementation work.
• Collaborate with architecture, RTL, verification, DFT and package teams.
• Manage foundry, IP and backend-services partners.

Skills

ASIC physical design

Tapeout leadership

RTL-to-GDSII flow

Cadence tools

Synopsys tools

Floorplanning

Timing closure

Clock distribution

Power integrity

Physical verification

Tcl & Python

Communication skills

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree or PhD in Electrical/Computer Engineering

Tools

Cadence Genus/Innovus/Quantus/Tempus

Synopsys Fusion Compiler/ICC2/StarRC/PrimeTime

Job description

Alpaca Research in Cambridge, MA seeks a Staff Physical Design Engineer to own ASIC implementation from floorplanning to tapeout. This on-site role requires leading full-chip timing, power, and signoff, mentoring the team and coordinating with foundry and backend partners.

The candidate will drive RTL-to-GDSII flow, macro placement, clock distribution, power integrity, and physical verification for advanced nodes, using Cadence or Synopsys toolchains. Excellent communication is essential.