Senior ASIC Physical Design Engineer – Top-Level

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 183,000 - 248,000; Full time

Job summary

Annapurna Labs, part of Amazon, seeks an ASIC Physical Design Engineer in Cupertino to drive floorplanning, placement, integration, and tapeout for advanced SoCs. You will collaborate with the FE team to translate RTL into robust physical designs, and lead DV/verification using Calibre, IC Validator and PVS across processes.

The role requires 5+ years in physical verification, scripting, and strong communication. Experience with FC/Innovus flows and mentoring is preferred.

Qualifications

• BS + 10yrs or MS + 7yrs in EE/CS, or related field.
• 5+ in physical verification for advanced technology nodes.
• Design Flow Knowledge: Backend physical design flows for chip-top/subsystems (FC/Innovus).
• Expert knowledge of physical verification tools (Calibre, IC Validator, PVS).
• Strong understanding of semiconductor manufacturing processes and design rules.

Responsibilities

• Drive full chip floorplan, placement, integration, PV signoff and tapeout.
• Collaborate with FE team to understand RTL and drive physical aspects early in design cycle.
• Define, execute and optimize next-generation physical verification methodologies using industry-standard EDA tools (FC, Calibre, IC Validator).
• Perform DRC, LVS, PERC verification.
• Debug and resolve physical verification issues with layout and design teams.
• Interface with foundries for MT form, rule deck updates and violation waivers; develop verification runsets.
• Mentor junior engineers on physical verification methodologies and closure.

Skills

Scripting with Python

Backend physical design knowledge

Physical verification

Communication skills

Tape-out experience

Collaboration

Education

BS + 10yrs or MS + 7yrs in EE/CS

Tools

Calibre

IC Validator

PVS

FC

Innovus

Job description

Annapurna Labs, part of Amazon, seeks an ASIC Physical Design Engineer in Cupertino to drive floorplanning, placement, integration, and tapeout for advanced SoCs. You will collaborate with the FE team to translate RTL into robust physical designs, and lead DV/verification using Calibre, IC Validator and PVS across processes.

The role requires 5+ years in physical verification, scripting, and strong communication. Experience with FC/Innovus flows and mentoring is preferred.