ASIC Physical Design Engineer — New Graduate (MS/PhD)

Alpaca Research; Cambridge (MA); On-site; USD 150,000 - 210,000; Full time

Job summary

Alpaca Research is hiring for a full‑time, on‑site ASIC physical design role in Cambridge, MA. You will contribute to the physical implementation of Alpaca's ASIC designs, from synthesis through place and route and timing closure, starting with defined blocks and growing ownership as you gain experience.

The role emphasizes strong fundamentals in digital IC design, VLSI, and proficiency in Python and Tcl, with collaboration across silicon, RTL, and architecture teams. 2027 start for onsite work.

Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering or related field, expected Dec 2026–Jun 2027.
• Hands-on ASIC physical design experience from research, coursework or internship with ownership of implementation and debugging.
• Experience taking RTL/netlist through place & route to DRC-clean layout and timing closure using Cadence, Synopsys or Open-source tools.
• Strong foundations in digital IC design, VLSI, CMOS logic, synchronous design, clocking and interconnect delay.
• Programming in Python and Tcl; comfortable with Linux.
• Strong analytical and debugging skills with ability to explain results and tradeoffs clearly.

Responsibilities

• Implement blocks through synthesis, floorplanning, placement, clock-tree synthesis and routing; use static timing to guide closure.
• Analyze timing, congestion, area and power; implement changes and measure effects.
• Write Tcl and Python scripts to automate steps, reproduce runs and summarize results.
• Contribute to SRAM macro placement, power-grid planning and physical verification for memory-intensive blocks.
• Collaborate with RTL, verification and architecture engineers to understand design choices on physical implementation.
• Document results, participate in design reviews, and take increasing responsibility for block deliverables.

Skills

Digital IC design

VLSI

Python

Tcl

Linux

Analytical thinking

Debugging

Education

Master's or PhD in Electrical/Computer Engineering

Tools

Cadence

Synopsys

OpenROAD

OpenSTA

Yosys

KLayout

Magic

Job description

Who we are

Today, AI is something you rent. Alpaca is building the full stack of hardware, software, models, and applications together to make it something you own.

We are developing a new computer architecture that breaks the economics keeping frontier models trapped in datacenters. On top of that, we’re building a platform of models, applications, and services that give that hardware meaning.

Personal AI is moving from the datacenter to the desk, and we are driving that change.

Our team is based in Cambridge, MA.

About the role

We are looking for master's and PhD graduates with strong fundamentals in digital IC design and substantial hands‑on experience in ASIC physical implementation through research, internships or tapeout projects.

You will contribute to the physical implementation of Alpaca's ASIC designs, from synthesis through place and route and timing closure. Starting with well‑defined blocks, you will analyze timing, congestion and power, implement improvements, and develop scripts that make the design flow reproducible. You will work closely with the silicon team and take increasing ownership of block implementation as you build experience.

This is a full‑time, on‑site role at our Cambridge office, starting in 2027.

Minimum qualifications

• A master's degree or PhD in Electrical Engineering, Computer Engineering or a related field, completed or expected between December 2026 and June 2027.

• Substantial hands‑on ASIC physical design experience through research, coursework or an internship, with clear personal responsibility for implementation and debugging.

• Experience taking a design from RTL or a netlist through place and route to a DRC‑clean layout and closing timing, using Cadence, Synopsys or an open‑source flow such as OpenROAD.

• Strong foundations in digital IC design, VLSI and computer architecture, including CMOS logic, synchronous design, setup and hold timing, clocking and interconnect delay.

• Programming skills in Python and Tcl, and comfort working in Linux.

• Strong analytical and debugging skills, with the ability to explain implementation results, design tradeoffs and your own contributions clearly.

Preferred qualifications

• Contributions to a chip tapeout, with clear ownership of physical implementation tasks.

• Research in VLSI, physical design, EDA or computer architecture involving implemented and evaluated designs or tools.

• An internship in physical design, timing, verification or CAD.

• Experience with SRAM macros, power‑grid planning, physical verification (DRC/LVS) or low‑power design.

• Experience with open‑source tools such as OpenROAD, Yosys, OpenSTA, KLayout or Magic.

What you will do

• Implement assigned blocks through synthesis, floorplanning, placement, clock‑tree synthesis and routing, using static timing analysis to guide timing closure.

• Analyze timing, congestion, area and power results; implement changes and measure their effects.

• Write Tcl and Python scripts to automate implementation steps, reproduce runs and summarize results.

• Contribute to SRAM macro placement, power‑grid planning and physical verification for memory‑intensive blocks.

• Work with RTL, verification and architecture engineers to understand how design choices affect physical implementation.

• Document results and unresolved issues, participate in design reviews, and take increasing responsibility for block deliverables.