Senior ASIC Physical Design Engineer - San Jose, CA (100% Onsite) - FTE Permanent role - AS

Central Business Solutions, Inc; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Central Business Solutions, Inc. in San Jose, CA seeks a Senior ASIC Physical Design Engineer for a 100% onsite, permanent role. The position focuses on advancing AI designs by driving the physical design from netlist to silicon tape-out.

Responsibilities include timing closure, place and route, EM/IR analysis, clock tree synthesis, floorplanning, and collaboration with RTL engineers. A strong TCL/Perl scripting background and deep EDA tool knowledge are required.

Qualifications

• Bachelor's degree in Electrical Engineering or Electronics Engineering.
• 8+ years of relevant ASIC physical design experience.
• Full physical design cycle experience from RTL to Tape-out.
• Strong verbal and written communication skills.

Responsibilities

• Execute Physical Design, Physical Verification, and Timing Closure.
• Achieve timing closure through various methods; top-level STA experience preferred.
• EM/IR Analysis, Place and Route.
• Clock Tree Synthesis; custom clock trees, insertion reduction and skew balancing techniques.
• Floor-planning and Layout; top-level floorplanning experience.
• Develop flows and methodologies.
• Collaborate with IC Design RTL Engineers.

Skills

TCL scripting

PERL scripting

Verilog/VHDL knowledge

Communication skills

Education

Bachelor's degree in Electrical/Electronics Engineering

Tools

EDA tools proficiency

Job description

Senior ASIC Physical Design Engineer - San Jose, CA (100% Onsite) - FTE Permanent role - AS

San Jose, CA

Title: Senior ASIC Physical Design Engineer
Location: San Jose, CA (100% Onsite)
Location for the role is on-site at San Jose, 5-days a week
Type: FTE Permanent role

Job Description:
Client is searching for a Physical Design Engineer to join the ASIC Products Division. This position involves working with the latest technology to continue driving next generation AI designs. This position will require in-depth knowledge and expertise in Physical Design aspects of taking Netlist to silicon tape-out.

Responsibilities include, but are not limited to the following:

• Execution of Physical Design, Physical Verification, and Timing Closure
• Timing closure through various methods and strategies; preferable in-depth experience in top-level STA
• EM/IR Analysis, Place and Route
• Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques
• Floor-planning and Layout; preferable in-depth experience in top-level floorplanning
• Flow and Methodology Development
• Collaborating with IC Design RTL Engineers

Required attributes:

• TCL/PERL Scripting
• Proficiency in related EDA Tools
• Full physical design cycle experience: RTL to Tape-out
• Excellent verbal and written communication skills

Education and Experience Requirements:

• Minimum: Bachelor 0 a0degree required in Electrical Engineering or Electronics Engineering
• 8+ Years of relevant experience