Staff ASIC Physical Design Engineer

Alpaca Research; Cambridge (MA); On-site; USD 300,000 - 350,000; Full time

Job summary

Alpaca Research in Cambridge, MA seeks a Staff Physical Design Engineer to own ASIC implementation from floorplanning to tapeout. This on-site role requires leading full-chip timing, power, and signoff, mentoring the team and coordinating with foundry and backend partners.

The candidate will drive RTL-to-GDSII flow, macro placement, clock distribution, power integrity, and physical verification for advanced nodes, using Cadence or Synopsys toolchains. Excellent communication is essential.

Qualifications

• 8+ years of hands-on ASIC physical design experience.
• Multiple tapeouts with top-level physical signoff responsibility.
• Experience at 16 nm or smaller FinFET nodes.
• Proficiency in RTL-to-GDSII flow with Cadence or Synopsys toolchains.
• Strong Tcl and Python scripting for flows.
• Clear communication of implementation results to architects and leadership.

Responsibilities

• Own full-chip floorplan and partitioning, SRAM macro placement, I/O and bump planning with the package team.
• Set area, timing and power budgets for each partition.
• Lead top-level implementation: clock distribution, power-grid design, and integration of blocks and hard IP.
• Own chip-level timing constraints and signoff across modes and corners, including ECOs.
• Define and maintain reproducible implementation methodology for the team.
• Mentor physical-design engineers and review implementation work.
• Collaborate with architecture, RTL, verification, DFT and package teams.
• Manage foundry, IP and backend-services partners.

Skills

ASIC physical design

Tapeout leadership

RTL-to-GDSII flow

Cadence tools

Synopsys tools

Floorplanning

Timing closure

Clock distribution

Power integrity

Physical verification

Tcl & Python

Communication skills

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree or PhD in Electrical/Computer Engineering

Tools

Cadence Genus/Innovus/Quantus/Tempus

Synopsys Fusion Compiler/ICC2/StarRC/PrimeTime

Job description

Compensation:

$300,000 - $350,000 + Equity

Who we are

Today, AI is something you rent. Alpaca is building the full stack of hardware, software, models, and applications together to make it something you own.

We are developing a new computer architecture that breaks the economics keeping frontier models trapped in datacenters. On top of that, we’re building a platform of models, applications, and services that give that hardware meaning.

Personal AI is moving from the datacenter to the desk, and we are driving that change.

Our team is based in Cambridge, MA.

About the role

We are looking for a Staff Physical Design Engineer to own the physical implementation of Alpaca's ASIC designs, from early floorplan studies through tapeout. You will define the implementation methodology and flow, set the chip's floorplan and partitioning, lead timing, power-integrity and physical signoff, and coordinate implementation work with foundry and backend-services partners. You will also mentor the engineers who join the physical-design team.

This is a full-time, on-site role at our Cambridge office.

• Bachelor's degree in Electrical Engineering, Computer Engineering or a related field, or equivalent practical experience.
• 8+ years of hands-on ASIC physical design experience.
• Multiple tapeouts of designs that reached working silicon, including at least one where you led full-chip or top-level physical implementation and were responsible for signoff.
• Implementation experience at FinFET nodes (16 nm or below).
• Expertise in the complete RTL-to-GDSII flow (synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, timing closure and ECOs) in Cadence (Genus, Innovus, Quantus, Tempus) or Synopsys (Fusion Compiler, ICC2, StarRC, PrimeTime) tools.
• Floorplanning and partitioning of large, macro-dominated designs: macro placement, channel and pin-access planning, congestion analysis, and partition timing and area budgets.
• Signoff-level static timing analysis: writing and reviewing constraints and exceptions (generated clocks, false and multicycle paths, clock-domain crossings), multi-mode multi-corner analysis, on-chip variation (AOCV/POCV) and signal-integrity effects.
• Clock-distribution design: skew, latency and power tradeoffs across a full chip.
• Power-grid design with static and dynamic IR-drop and electromigration signoff.
• Physical-verification closure at advanced nodes: DRC, LVS, antenna, density and ERC.
• Strong Tcl and Python skills, including building implementation flows used by other engineers.
• Clear, precise communication of implementation results, risks and tradeoffs to architects and company leadership.

Preferred qualifications

• Master's degree or PhD in Electrical or Computer Engineering.
• Implementation experience at 7 nm or below.
• SRAM macro integration; memory compilers and their timing and physical views.
• Low-power implementation with UPF: multiple power domains, power gating, isolation and level shifting.
• Physical impact of DFT: scan insertion and compression, MBIST.
• Managing foundry, IP or backend-services partners and accepting their deliverables.
• Silicon bring-up and correlation of silicon results with implementation models.
• Mentoring or leading a physical-design team.
• Background in complex digital ASICs or SoCs.

Responsibilities

• Own the full-chip floorplan and partitioning, including SRAM macro placement, I/O and bump planning with the package team, and congestion analysis.
• Run physical feasibility studies during architecture development and set area, timing and power budgets for each partition.
• Lead top-level implementation: clock distribution, power-grid design, and integration of blocks and hard IP.
• Own chip-level timing constraints and signoff across all modes and corners, through ECO closure.
• Own power-integrity and physical-verification signoff, and the physical signoff package for tapeout.
• Define and maintain a reproducible, scripted implementation methodology for the team.
• Help select and manage foundry, IP and backend-services partners, and review their deliverables against our acceptance criteria.
• Mentor physical-design engineers and review their implementation work.
• Work closely with architecture, RTL, verification, DFT and package engineers.