Senior ASIC Physical Design Engineer – Drive Next-Gen SoCs

Amazon; Cupertino (CA); On-site; USD 213,000 - 288,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino is seeking an ASIC Physical Design Engineer to design and optimize hardware for AWS data center solutions.

You will collaborate with RTL/Arch teams to drive architectural feasibility, perform floorplanning, synthesis, and timing closure, and evaluate third-party IP to ensure high design quality. The role requires a strong background in ASIC physical design from RTL to GDSII across multiple process nodes, with expertise in CAD flows and sign-off activities.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering.
• BS + 8yrs or MS + 6yrs in EE/CS.
• Experience scripting with Python, Perl, Bash or PowerShell.
• 6+ years in ASIC Physical Design from RTL-to-GDSII in 7nm/14/16nm/20nm/28nm.
• Block Design using EDA tools including synthesis, ECO, floor planning, place and route.

Responsibilities

• Work with RTL/logic designers to drive architectural feasibility studies and power-performance tradeoffs.
• Drive IO/Core subsystem physical implementation through synthesis, floor planning, place and route, sign-off.
• Develop physical design methodologies.
• Evaluate 3rd party IP and provide recommendations.
• Collaborate with physical design and RTL/Arch teams.

Skills

Scripting languages

ASIC Physical Design

RTL-to-GDSII flows

Education

Bachelor's degree in EE/CS/CE

BS+8yrs or MS+6yrs experience

Tools

Cadence

Mentor Graphics

Synopsys

Job description

Annapurna Labs (U.S.) Inc. in Cupertino is seeking an ASIC Physical Design Engineer to design and optimize hardware for AWS data center solutions.

You will collaborate with RTL/Arch teams to drive architectural feasibility, perform floorplanning, synthesis, and timing closure, and evaluate third-party IP to ensure high design quality. The role requires a strong background in ASIC physical design from RTL to GDSII across multiple process nodes, with expertise in CAD flows and sign-off activities.