Senior ASIC Timing & Physical Design Engineer (Equity)

NVIDIA Corporation; Westford (MA); On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA Corporation in Massachusetts seeks a Senior ASIC Timing Design Engineer to drive timing for high-frequency DPUs/SoCs across block to full-chip levels. You will optimize constraints, manage ECO-led timing closure, and push RTL-to-GDS2 through front-end and back-end stages.

Ideal candidates have strong STA, ECO, Lean EDA tooling expertise (PrimeTime/Tempus) and scripting with Python, Tcl, and Make. Compensation includes base salary, equity, and benefits.

Qualifications

• BS or MS in Electrical or Computer Engineering with required years of experience.
• Hands-on STA, timing constraints generation and management.
• Experience in ECOs and timing convergence for front-end and back-end flows.

Responsibilities

• Drive physical design and timing of high-frequency DPUs and SoCs.
• Analyze constraints and synthesis parameters to meet perf/area targets.
• Guide RTL to GDS2 flow including ECO implementation and timing convergence.

Skills

STA

Synthesis

Timing convergence

ECOs

LEC

EDA tools

Python

Tcl & Make

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

NVIDIA Corporation in Massachusetts seeks a Senior ASIC Timing Design Engineer to drive timing for high-frequency DPUs/SoCs across block to full-chip levels. You will optimize constraints, manage ECO-led timing closure, and push RTL-to-GDS2 through front-end and back-end stages.

Ideal candidates have strong STA, ECO, Lean EDA tooling expertise (PrimeTime/Tempus) and scripting with Python, Tcl, and Make. Compensation includes base salary, equity, and benefits.