Senior ASIC Package Designer – High-Speed SerDes & SI/PI

Anysilicon; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Broadcom in San Jose, CA is seeking an experienced IC package-design engineer to develop complex flip-chip‑BGA packages for high-performance ASICs, focusing on AI, networking, high-performance computing, and 5G base stations.

You will lead signal integrity, power integrity, and thermal considerations, design critical SerDes, DDR, and HBM structures, and manage multiple projects with global teams. Strong Cadence/APD proficiency and cross‑zone collaboration are required.

Qualifications

• BSEE or MSEE with extensive flip-chip-BGA package design experience and high-speed SerDes.
• Knowledge of package-level signal integrity and power integrity for package designs.
• Experience with Cadence APD or equivalent tools; co-design with global teams.

Responsibilities

• Own ASIC package designs focusing on SI, PI, manufacturability, reliability and thermal.
• Design critical structures for SerDes, DDR, HBM, ADC/DAC, etc.
• Coordinate schedules, priorities and progress across multiple projects.
• Act as project manager and customer interface for design projects.
• Improve efficiency via process development, automation, and documentation.
• Perform physical design (layout) as a core duty.

Skills

Signal integrity

Power integrity

Project management

Cadence APD (Allegro)

Education

BSEE or similar field with 12 years of experience in flip-chip-BGA package design, including high-speed SerDes

MSEE with 10 years of experience

Tools

Cadence APD (Allegro)

Job description

Broadcom in San Jose, CA is seeking an experienced IC package-design engineer to develop complex flip-chip‑BGA packages for high-performance ASICs, focusing on AI, networking, high-performance computing, and 5G base stations.

You will lead signal integrity, power integrity, and thermal considerations, design critical SerDes, DDR, and HBM structures, and manage multiple projects with global teams. Strong Cadence/APD proficiency and cross‑zone collaboration are required.