Senior ASIC Package Design Engineer — SerDes/BGA (On-Site)

Broadcom Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Annual bonus

Equity grants/awards

Medical, dental & vision

Job summary

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages used in AI, networking, HPC, and 5G base stations. You will lead ASIC package designs with a focus on signal integrity, power integrity, reliability, and thermal management.

Requirements include 12+ years in flip-chip-BGA design (BSEE) and 10+ years for MS-based candidates, plus Cadence/APD experience. On-site at Broadcom, with strong cross-time-zone collaboration across a global R&D team.

Qualifications

• BSEE or equivalent with 12+ years in flip-chip-BGA package design including high-speed SerDes.
• MSEE or equivalent with 10+ years of work experience.
• Knowledge of package-level signal integrity and power integrity; Cadence APD/Allegro experience preferred.

Responsibilities

• Overall design responsibility for ASIC package designs, including SI/PI, manufacturability, reliability, and thermal.
• Package design of critical structures for SerDes, ADC/DAC, DDR, HBM, etc.
• Schedule, prioritize, and track your work across 2+ projects simultaneously.
• General flip-chip BGA package design and engineering
• Project management and customer interface for your design projects
• Contribute to efficiency improvements for the design team through process dev/improvement, automation, documentation, etc.
• Physical design (layout) is a foundational responsibility in this role

Skills

Self-management

Organization skills

Team collaboration

Education

BSEE or similar field

MSEE or similar field

Tools

Cadence APD

Allegro package designer

Cadence SKILL

Job description

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages used in AI, networking, HPC, and 5G base stations. You will lead ASIC package designs with a focus on signal integrity, power integrity, reliability, and thermal management.

Requirements include 12+ years in flip-chip-BGA design (BSEE) and 10+ years for MS-based candidates, plus Cadence/APD experience. On-site at Broadcom, with strong cross-time-zone collaboration across a global R&D team.