ASIC Package Design Engineer

Anysilicon; San Jose (CA); Presencial; USD 150.000 - 210.000; Jornada completa

Descripción de la vacante

Broadcom in San Jose, CA is seeking an experienced IC package-design engineer to develop complex flip-chip‑BGA packages for high-performance ASICs, focusing on AI, networking, high-performance computing, and 5G base stations.

You will lead signal integrity, power integrity, and thermal considerations, design critical SerDes, DDR, and HBM structures, and manage multiple projects with global teams. Strong Cadence/APD proficiency and cross‑zone collaboration are required.

Formación

• BSEE or MSEE with extensive flip-chip-BGA package design experience and high-speed SerDes.
• Knowledge of package-level signal integrity and power integrity for package designs.
• Experience with Cadence APD or equivalent tools; co-design with global teams.

Responsabilidades

• Own ASIC package designs focusing on SI, PI, manufacturability, reliability and thermal.
• Design critical structures for SerDes, DDR, HBM, ADC/DAC, etc.
• Coordinate schedules, priorities and progress across multiple projects.
• Act as project manager and customer interface for design projects.
• Improve efficiency via process development, automation, and documentation.
• Perform physical design (layout) as a core duty.

Conocimientos

Signal integrity

Power integrity

Project management

Cadence APD (Allegro)

Educación

BSEE or similar field with 12 years of experience in flip-chip-BGA package design, including high-speed SerDes

MSEE with 10 years of experience

Herramientas

Cadence APD (Allegro)

Descripción del empleo

Broadcom is seeking an experienced IC package-design engineer to develop complex flip-chip-BGA packages for high-performance ASICs, focusing on applications in artificial intelligence, networking, high-performance computing, and 5G base stations. The role involves collaboration with a global R&D team to create innovative package structures that meet high-speed and power delivery requirements.

Responsibilities:

• Overall design responsibility for ASIC package designs, focusing on signal integrity, power integrity, manufacturability, reliability, and thermal aspects.
• Design critical structures for SerDes, ADC/DAC, DDR, HBM, etc.
• Manage schedules, prioritize tasks, and track progress across multiple projects simultaneously.
• Act as project manager and customer interface for design projects.
• Contribute to efficiency improvements through process development, automation, and documentation.
• Perform physical design (layout) as a foundational responsibility.

Qualifications:

• BSEE or similar field with 12 years of experience in flip-chip-BGA package design, including high-speed SerDes, or MSEE with 10 years of experience.
• Knowledge of package-level signal integrity and power integrity for application in package designs.
• Experience with Cadence APD (Allegro Package Designer) preferred, or equivalent tools.
• Ability to collaborate with a worldwide team across multiple time zones, including co-design with internal and external designers.
• Strong self-management and organizational skills.
• Preferred: 1+ years of experience with Cadence SKILL for Allegro or similar design-automation coding experience.

Skills:

• Signal integrity
• Power integrity
• Project management
• Cadence APD (Allegro)

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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