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Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages used in AI, networking, HPC, and 5G base stations. You will lead ASIC package designs with a focus on signal integrity, power integrity, reliability, and thermal management.
Requirements include 12+ years in flip-chip-BGA design (BSEE) and 10+ years for MS-based candidates, plus Cadence/APD experience. On-site at Broadcom, with strong cross-time-zone collaboration across a global R&D team.
Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 448G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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