Lead ASIC Package Design PM for High-Speed AI/HPC

Hardware FYI; Fort Collins (CO); Híbrido; USD 120.000 - 180.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, vision

401(K) with company match

Employee stock purchase program

Descripción de la vacante

Broadcom is seeking an experienced IC Package Design Project Manager to lead a team of engineers in designing complex flip-chip-BGA packages for high-speed SerDes and high-power delivery needs. The role involves global collaboration across AI, networking, HPC, and 5G programs, with opportunities to contribute to technical methodologies.

Responsibilities include planning 20+ concurrent designs, improving scheduling, and ensuring on-time delivery while aligning with design rules and

Formación

• Bachelor's degree required with 12+ years of related experience or Master's with 10+ years.
• Experience managing package design projects.
• Knowledge of package-level signal integrity and power integrity.
• Cooperation with worldwide team across time zones; internal and external designers.
• Strong self-management and organizational skills.
• Technical understanding of package design lifecycle and manufacturing flows.

Responsabilidades

• Create and track project plans for 20+ concurrent designs (scope, schedules, resources)
• Improve scheduling methodologies and task tracking and coordination
• Organize team and customer activities to keep projects on track
• Communicate plans, status, next steps and risks
• Create technical methodologies for package design
• Steer package technology and design rules with team input
• Collaborate with customers, vendors, and cross-functional teams

Conocimientos

Package design

Project management

SI/PI analysis

Cross-functional collaboration

Automation coding

Mechanical & Thermal modeling

Educación

Bachelor's degree

Master's degree

Herramientas

CAD tools

Package drawings tools

Descripción del empleo

Broadcom is seeking an experienced IC Package Design Project Manager to lead a team of engineers in designing complex flip-chip-BGA packages for high-speed SerDes and high-power delivery needs. The role involves global collaboration across AI, networking, HPC, and 5G programs, with opportunities to contribute to technical methodologies.

Responsibilities include planning 20+ concurrent designs, improving scheduling, and ensuring on-time delivery while aligning with design rules and