Package Design Engineer - High-Speed SerDes for AI ASICs

Broadcom Inc.; San Jose (CA); Hybrid; USD 83,000 - 132,000; Full time

Benefits offered by this job

Discretionary bonus

Annual equity awards

Comprehensive benefits

Job summary

Broadcom Inc. is seeking an IC package-design engineer for complex flip-chip-BGA packages to support AI, networking, HPC and 5G base stations. You will join a worldwide R&D team to develop high-performance package designs for ASICs with 224G SerDes and high-power delivery.

The role emphasizes physical design, signal integrity, power integrity and reliability, with project management across 2+ concurrent projects. This is an on-site position at Broadcom, five days a week.

Qualifications

• BSEE or similar field and 2+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or PhD.
• Knowledge of electrical engineering fundamentals.
• Cadence APD experience preferred; equivalent layout tool OK.
• Cooperate with our world-wide team across multiple time zones.
• 1+ year experience with Cadence SKILL or similar design-automation coding.

Responsibilities

• Overall design responsibility for ASIC package designs, including signal integrity, power integrity, manufacturability, reliability, and thermal.
• Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
• Schedule, prioritize, and track your work across 2+ projects simultaneously.
• General flip-chip BGA package design and engineering.
• Project management and customer interface for design projects.
• Contribute to efficiency improvements through process development, automation, and documentation.
• Physical design (layout) as a foundational responsibility.

Skills

Electrical engineering fundamentals

Self-management

Global collaboration

Education

BSEE or MS/PhD in related field

Tools

Cadence APD

Allegro

Cadence SKILL

Job description

Broadcom Inc. is seeking an IC package-design engineer for complex flip-chip-BGA packages to support AI, networking, HPC and 5G base stations. You will join a worldwide R&D team to develop high-performance package designs for ASICs with 224G SerDes and high-power delivery.

The role emphasizes physical design, signal integrity, power integrity and reliability, with project management across 2+ concurrent projects. This is an on-site position at Broadcom, five days a week.