Senior ASIC Implementation Lead — Low-Power UPF & RTL

Socket.dev; Sunnyvale (CA); On-site; USD 159,000 - 248,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

RSU/sign-on bonuses

Job summary

Amazon is seeking an experienced Senior ASIC Implementation Lead in California to define and implement power aware chip strategies. You will collaborate with ASIC, RFIC, and P&R teams to ensure clean synthesis, robust timing, and correct physical integration for high-volume satellite communications chips.

The role emphasizes leading UPF-driven flows, RTL/netlist validation, and rigorous sign-off processes, with responsibilities across multiple nodes and power islands.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 7+ years of ASIC implementation experience including synthesis, STA and P&R for deep sub-micron nodes (16nm+).
• Experience leading or developing methodologies and scripts for physical synthesis.
• Track record taping out chips into high-volume production.
• Experience with multiple power islands and power gating.

Responsibilities

• Define and implement chip power intent using UPF with ASIC team.
• Validate UPF at RTL and netlist level using industry tools.
• Set up flow for logic and physical synthesis across technology nodes.
• Develop implementation methodologies including AI-assisted flows.
• Create timing constraints with ASIC and DFT teams.
• Verify RTL and netlist; perform STA and LEC checks.
• Coordinate RFIC integration and block-level connectivity checks.
• Collaborate with P&R teams to hand off netlists and ensure timely P&R execution.
• Lead timing sign-off for post P&R database.
• Verify DFM criteria using IR/EM results.

Skills

Leading physical design

UPF flow

Synthesis & STA

Education

Bachelor's degree in Electrical Engineering or related field

Master's or Ph.D in Electrical/Communications Engineering

Tools

UPF flow

Job description

Amazon is seeking an experienced Senior ASIC Implementation Lead in California to define and implement power aware chip strategies. You will collaborate with ASIC, RFIC, and P&R teams to ensure clean synthesis, robust timing, and correct physical integration for high-volume satellite communications chips.

The role emphasizes leading UPF-driven flows, RTL/netlist validation, and rigorous sign-off processes, with responsibilities across multiple nodes and power islands.