Senior ASIC Physical Design Engineer - Space-Grade SoCs

Amazon; San Diego (CA); On-site; USD 159,000 - 215,000; Full time

Benefits offered by this job

Health insurance

RSUs

401(k) matching

Paid time off

Parental leave

Job summary

Amazon is seeking a Sr. Physical Design Engineer for the Amazon Leo project in San Diego to drive architectural feasibility and physical implementation across RTL and back-end flows. You will evaluate IP, optimize power-perf-area, and collaborate with RTL/Arch teams to deliver high‑quality SOCs for satellite communications.

The role emphasizes leadership in physical design methodology and multi‑site teamwork, with a strong focus on modern CMOS nodes and AI‑assisted flows.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering.
• 7+ years of experience in ASIC implementation, i.e., synthesis, STA and working with DFT, P&R for deep sub‑micron nodes.

Responsibilities

• Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure
• Drive IO/Core block physical implementation through synthesis, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off
• Develop physical design methodologies while embracing AI flow
• Evaluate 3rd party IP and provide recommendations
• Be a highly-valued member of our start‑up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams

Skills

ASIC implementation

Synthesis

STA

DFT

Place & Route

Power analysis

Collaboration

AI/ML flows

Education

Bachelor's in EE/CE/CS

Master's in EE/Communications

Tools

UPF flow

Job description

Amazon is seeking a Sr. Physical Design Engineer for the Amazon Leo project in San Diego to drive architectural feasibility and physical implementation across RTL and back-end flows. You will evaluate IP, optimize power-perf-area, and collaborate with RTL/Arch teams to deliver high‑quality SOCs for satellite communications.

The role emphasizes leadership in physical design methodology and multi‑site teamwork, with a strong focus on modern CMOS nodes and AI‑assisted flows.