Senior ASIC Physical Design Engineer - AI-Driven Flows

Socket.dev

San Diego (CA)

On-site

USD 159,000 - 215,000

Full time

9 days ago

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Benefits offered by this job

Health insurance
401(k) matching
Paid time off
Parental leave
RSUs

Job summary

Amazon Leo is building a constellation of LEO satellites to deliver low-latency broadband globally. The role defines and implements digital chip SOCs for communications via satellites, working with RTL/Arch teams to design modems, high-speed interfaces, embedded processors, and DSP solutions in cutting-edge CMOS tech.

Bachelor’s in CS/CE/EE required with 7+ years in ASIC, including synthesis and P&R; Master’s preferred with RF/Analog/Mixed signal experience; UPF and multi-site collaboration are

Qualifications

  • Bachelor's degree in CS/CE/EE required, with 7+ years in ASIC implementation.
  • Experience in synthesis, STA, DFT and P&R for deep sub-micron nodes.
  • Preferred Master’s degree and ML/AI exposure.

Responsibilities

  • Collaborate with RTL/logic designers on architectural feasibility and tradeoffs.
  • Drive IO/Core block physical implementation through synthesis and place & route.
  • Develop physical design methodologies incorporating AI flows.
  • Evaluate third-party IP and provide recommendations.
  • Collaborate across teams to deliver integrated RF/Analog/Digital flows.

Skills

ASIC implementation
Synthesis
STA
DFT
P&R
Physical design
UPF flow
RF/Analog/Mixed signal integration

Education

Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering
Master's degree in Electrical or Communications Engineering

Tools

Managed ML/AI solutions

Job description

Amazon Leo is building a constellation of LEO satellites to deliver low-latency broadband globally. The role defines and implements digital chip SOCs for communications via satellites, working with RTL/Arch teams to design modems, high-speed interfaces, embedded processors, and DSP solutions in cutting-edge CMOS tech.

Bachelor’s in CS/CE/EE required with 7+ years in ASIC, including synthesis and P&R; Master’s preferred with RF/Analog/Mixed signal experience; UPF and multi-site collaboration are

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