Senior ASIC Implementation Engineer – Timing, P&R & Power

Broadcom; Irvine (CA); On-site; USD 127,000 - 203,000; Full time

Benefits offered by this job

Discretionary bonus

Equity grants

401(K) with match

ESPP

Paid holidays

Paid time off

Job summary

Broadcom in Irvine, CA seeks an experienced ASIC Implementation Engineer to lead multiple design disciplines through synthesis, floorplanning, place-and-route, timing closure, and sign-off. The role requires deep expertise with EDA tools and scalable collaboration with global teams.

Ideal candidates hold a Bachelor’s degree with 12+ years (or higher) in related roles, and are prepared to drive peer reviews, optimize power and performance, and ensure quality across complex IC implementations.

Qualifications

• Bachelor's degree or higher with 12+ years of related ASIC experience or Master’s with 10+ years or PhD with 7+ years of related experience.
• Experience across multiple disciplines including synthesis, DFT, floorplanning, placement & routing, clocking, power, timing, SI, and physical design checks.
• Comfort leading design closure tasks and collaborating with distributed teams across geographies.

Responsibilities

• Participate in large complex design implementations using the latest technology nodes.
• Lead one or more disciplines in design closure as part of the design team.
• Have expertise in multiple EDA vendor solutions and be able to quickly adapt to changing requirements.
• Participate and drive peer reviews to ensure all quality requirements are met.
• Work with customers and design teams across multiple geographies.

Skills

Synthesis

Floorplanning

Place and route

Clock methodology

Power planning

Timing closure

Signal integrity

Physical design checks

Education

Bachelor's degree

Master's degree

PhD

Job description

Broadcom in Irvine, CA seeks an experienced ASIC Implementation Engineer to lead multiple design disciplines through synthesis, floorplanning, place-and-route, timing closure, and sign-off. The role requires deep expertise with EDA tools and scalable collaboration with global teams.

Ideal candidates hold a Bachelor’s degree with 12+ years (or higher) in related roles, and are prepared to drive peer reviews, optimize power and performance, and ensure quality across complex IC implementations.