Lead ASIC Design Engineer — RTL/SoC Architect

Technical-Link N. America; Brooklyn Park (MN); On-site; USD 140,000 - 210,000; Full time

Job summary

Technical-Link N. America seeks an ASIC Chip Lead and Design Engineer to drive the full chip design lifecycle from concept to implementation.

You will lead architecture, RTL, and physical design with a strong emphasis on area, power, and performance targets. The ideal candidate has 10+ years in ASIC/SoC design, hands-on RTL in Verilog/SystemVerilog, and extensive experience with Synopsys Design Compiler and EDA tools, plus exposure to radiation hardened and analog/mixed-signal design.

Qualifications

• Bachelors/Master’s in electrical engineering/computer science or equivalent.
• 10+ years of direct industry experience with ASIC and/or SoC design.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong understanding of digital design principles.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Excellent problem-solving skills and attention to detail.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Willingness to Mentor less senior engineers.

Responsibilities

• Lead the architectural design of ASICs based on high-level requirements and block diagrams.
• Collaborate with system architects to define chip functionality, interfaces, and performance targets.
• Develop detailed specifications for the chip’s components.
• Use Synopsys Design Compiler to create RTL designs and optimize for area, power, and performance.
• Develop timing constraints for the entire chip and work with physical design teams on floorplanning, placement, and routing.
• Constrain and verify RISC processors within the chip and optimize performance and power.
• Coordinate with verification engineers to ensure functional correctness and testbenches.

Skills

Unix/Linux

Shell scripting

C/C++

PERL/Python/TCL

Windows apps

Education

Bachelor's/Master's in EE/CS

Tools

Synopsys Design Compiler

EDA tools

Job description

Technical-Link N. America seeks an ASIC Chip Lead and Design Engineer to drive the full chip design lifecycle from concept to implementation.

You will lead architecture, RTL, and physical design with a strong emphasis on area, power, and performance targets. The ideal candidate has 10+ years in ASIC/SoC design, hands-on RTL in Verilog/SystemVerilog, and extensive experience with Synopsys Design Compiler and EDA tools, plus exposure to radiation hardened and analog/mixed-signal design.