SoC Power Design Engineer - Low-Power RTL and UPF

Nutanix; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks an ASIC Engineer focused on low-power design across SoC levels. You will work with frontend RTL, DFT, Synthesis, and Physical Design to implement and validate power intent (UPF) and related power models, contributing to power projections and clock/power analyses.

The role involves cross-functional collaboration with IP teams and CAD vendors to enhance power flows and ensure designs meet stringent low-power requirements across pre-silicon to post-silicon stages.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field with 4+ years in ASIC design/verification/validation.
• Master's or PhD degrees also considered with relevant ASIC experience.
• Experience with frontend RTL, DFT, synthesis, verification, and timing closure.
• Power-aware flow and low-power design using UPF/CPF; scripting in Perl/Tcl/Python.

Responsibilities

• Develop and validate low-power design intent at the SoC level.
• Collaborate with frontend RTL, DFT, Synthesis, and Physical Design teams.
• Review IP power features and ensure alignment with SoC budgets.
• Generate and validate UPF-based power intent designs for SoC.
• Engage with CAD/vendors to enhance power flows and tools.

Skills

ASIC frontend development

Logic design

RTL coding

Verification

Synthesis

Timing closure

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

UPF/CPF/Conformal

Verilog/VHDL/SystemVerilog

Perl/Tcl/Python

Job description

Qualcomm Technologies, Inc. seeks an ASIC Engineer focused on low-power design across SoC levels. You will work with frontend RTL, DFT, Synthesis, and Physical Design to implement and validate power intent (UPF) and related power models, contributing to power projections and clock/power analyses.

The role involves cross-functional collaboration with IP teams and CAD vendors to enhance power flows and ensure designs meet stringent low-power requirements across pre-silicon to post-silicon stages.