Senior ASIC Front-End Design Engineer (RTL & Verification)

Credo; San Jose (CA); On-site; USD 100,000 - 170,000; Full time

Benefits offered by this job

Equity

Medical benefits

Discretionary bonus

Job summary

Credo is seeking a Senior Design Engineer to own front-end ASIC design, including RTL implementation and verification of complex blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work with system teams for chip bring-up and validation.

The base salary range is $100,000 - $170,000 per year, with discretionary bonus, equity, and comprehensive medical benefits. Candidates should have a BS/MS in EE or CS and strong SystemVerilog proficiency.

Qualifications

• BS/MS in Electrical Engineering or Computer Science with five or more years of ASIC design experience.
• Strong understanding of digital logic design and complex interfaces.
• Proficiency in Verilog/SystemVerilog RTL design.
• Knowledge of synthesis and static timing analysis.
• Familiar with scripting languages: Python, Tcl, Perl, shell.

Responsibilities

• Design, implement, and debug complex logic blocks and integrate IPs.
• Support front-end integration activities: Lint, CDC, synthesis, and ECO.
• Participate in design and code reviews for quality assurance.
• Develop functional tests and testbenches; run RTL and gate-level simulations.
• Collaborate with verification, DFT, and physical design teams to tape-out and bring up features.

Skills

RTL design

Digital logic design

SystemVerilog

Python

Tcl

Perl

Shell

Education

BS/MS in Electrical Engineering or Computer Science

Job description

Credo is seeking a Senior Design Engineer to own front-end ASIC design, including RTL implementation and verification of complex blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work with system teams for chip bring-up and validation.

The base salary range is $100,000 - $170,000 per year, with discretionary bonus, equity, and comprehensive medical benefits. Candidates should have a BS/MS in EE or CS and strong SystemVerilog proficiency.