Senior Design Engineer

Credo; San Jose (CA); On-site; USD 100,000 - 170,000; Full time

Benefits offered by this job

Equity

Medical benefits

Discretionary bonus

Job summary

Credo is seeking a Senior Design Engineer to own front-end ASIC design, including RTL implementation and verification of complex blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work with system teams for chip bring-up and validation.

The base salary range is $100,000 - $170,000 per year, with discretionary bonus, equity, and comprehensive medical benefits. Candidates should have a BS/MS in EE or CS and strong SystemVerilog proficiency.

Qualifications

• BS/MS in Electrical Engineering or Computer Science with five or more years of ASIC design experience.
• Strong understanding of digital logic design and complex interfaces.
• Proficiency in Verilog/SystemVerilog RTL design.
• Knowledge of synthesis and static timing analysis.
• Familiar with scripting languages: Python, Tcl, Perl, shell.

Responsibilities

• Design, implement, and debug complex logic blocks and integrate IPs.
• Support front-end integration activities: Lint, CDC, synthesis, and ECO.
• Participate in design and code reviews for quality assurance.
• Develop functional tests and testbenches; run RTL and gate-level simulations.
• Collaborate with verification, DFT, and physical design teams to tape-out and bring up features.

Skills

RTL design

Digital logic design

SystemVerilog

Python

Tcl

Perl

Shell

Education

BS/MS in Electrical Engineering or Computer Science

Job description

About the role

As a Senior Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation.

Base salary range

Base salary range is $100,000 - $170,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

Why Credo

• Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People:Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what's next. Our technology powers the most reliable and energy-efficient connections around the world - and our team powers new products and markets that come next.

Basic Qualifications

• BS/MS degree in Electrical Engineering or Computer Science, with five or more years of relevant ASIC design experience.
• Strong understanding of digital logic design and complex synchronous/asynchronous interfaces.
• Proficiency in Verilog/SystemVerilog RTL design.
• Knowledge of synthesis and static timing analysis.

Preferred Qualifications

• Expertise in scripting languages (Python, Tcl, Perl, shell).
• Strong problem-solving and planning skills.
• Excellent communication and collaboration abilities.

Responsibilities

• Design, implement, and debug complex logic blocks, and integrate complex IPs from internal and external vendors.
• Support front-end integration activities such as Lint, CDC, synthesis, and ECO.
• Participate in design and code reviews to ensure quality.
• Develop functional tests and testbenches, and run RTL and gate-level simulations.
• Work with verification, DFT, and physical design engineers to achieve successful tape-outs; bring up, validate, and debug chip features, and collaborate with software, firmware, and systems teams.

About Credo

Credo's mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.

Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, gender identity, sexual orientation, pregnancy, marital status, national origin, ethnicity, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [e-mail].

Salary

100000 - 150000 USD (yearly)