Senior Front-End IC Design Engineer – ASIC & Verification

Broadcom Inc.; Austin (TX); On-site; USD 121,900 - 195,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(k) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

company paid holidays

paid sick leave and vacation time

Job summary

Broadcom Inc. in Austin, TX seeks a front end ASIC design engineer responsible for design blocks for cores, including architecture, logic design, synthesis, and verification. You will perform timing analysis and formal verification, simulate with Verilog, and ensure the ASIC flow from RTL to timing closure.

The role requires 8+ years (or 6+ with MS) and BS/MS in Electrical or Computer Engineering. occassional travel may be required; equity and bonuses are part of the package.

Qualifications

• BS/MS in Electrical or Computer Engineering or equivalent
• 8+ years of related experience; or Masters with 6+ years
• Experience with complete ASIC/standard product flow from RTL synthesis to timing closure
• Proficiency with TCL/Perl scripting, Synthesis tools, Primetime timing analysis, Liberty LIB models, Formal verification, Spyglass, Power analysis, DFT/scan, and version control

Responsibilities

• Front end design and verification of design blocks for the cores
• Architecture definition, logic design, synthesis, constraint development
• Verification through simulation and formal methods; timing analysis from physical implementation
• Design blocks from system requirements and simulate/debug with Verilog
• Familiarity with full ASIC design and implementation flow

Skills

RTL synthesis

Timing analysis

Formal verification

DFT / scan

Power analysis

Liberty LIB models

Verilog simulation

Version control

TCL/Perl scripting

Scripting / EDA

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Design Compiler

RTL Compiler

Primetime

Liberty LIB models

Formality

Conformal

Spyglass

svn/git

Power analysis

Job description

Broadcom Inc. in Austin, TX seeks a front end ASIC design engineer responsible for design blocks for cores, including architecture, logic design, synthesis, and verification. You will perform timing analysis and formal verification, simulate with Verilog, and ensure the ASIC flow from RTL to timing closure.

The role requires 8+ years (or 6+ with MS) and BS/MS in Electrical or Computer Engineering. occassional travel may be required; equity and bonuses are part of the package.