ASIC Digital Design Engineer with Equity & Bonus

Credo; San Jose (CA); On-site; USD 80,000 - 133,000; Full time

Job summary

Credo is hiring a Digital Design Engineer in California to lead front-end ASIC design, including complex logic and verification. You will work with Physical Design and Integration teams to enable successful tape-outs and deliver high-quality silicon.

The role emphasizes Verilog/SystemVerilog RTL, RTL verification, and scripting skills. Collaboration with software and systems teams is essential, and eligibility includes a base salary plus bonus/equity and comprehensive benefits.

Qualifications

• Bachelor's degree with 2–7 years of experience or Master's with up to 5 years in Electrical/Electronic or Computer Engineering.
• Understanding of digital logic design and complex synchronous/asynchronous interfaces.
• Knowledge of Verilog/SystemVerilog RTL design from coursework or experience.
• Knowledge of Verilog verification through coursework or projects.
• Knowledge of synthesis and static timing analysis; scripting with Python, Tcl, Perl and shell.

Responsibilities

• Write microarchitecture and design specifications; architect and implement complex logic blocks.
• Integrate IPs from internal/external vendors and support Lint, CDC, synthesis, and ECO.
• Develop functional tests and testbenches; run RTL and gate-level verification/simulations.
• Collaborate with ASIC, DFT, verification, and physical design to achieve tape-out.
• Coordinate with software/firmware teams to validate and debug chip features.

Skills

Digital logic design

Verilog/SystemVerilog

RTL verification

Scripting (Python Tcl Perl shell)

Interface handling (sync/async)

Education

Electrical/Electronic or Computer Engineering degree

Tools

UVM

Verilog/VHDL simulators

IEEE 802.3 Ethernet PHY

Job description

Credo is hiring a Digital Design Engineer in California to lead front-end ASIC design, including complex logic and verification. You will work with Physical Design and Integration teams to enable successful tape-outs and deliver high-quality silicon.

The role emphasizes Verilog/SystemVerilog RTL, RTL verification, and scripting skills. Collaboration with software and systems teams is essential, and eligibility includes a base salary plus bonus/equity and comprehensive benefits.