Senior RTL Design Engineer - SoC/IP Lead

Advanced Micro Devices, Inc.; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Advanced Micro Devices, Inc. is seeking a Senior ASIC Design Engineer for their Silicon Design team in San Jose, CA. The role involves owning the complete RTL design lifecycle and working on complex IP design for next-generation embedded products.

Candidates should have deep expertise in Verilog RTL coding and experience with the entire ASIC development process, including timing closure and SOC integration. The role promotes mentoring junior engineers and leading projects to successful completion.

Qualifications

• Proven experience across the entire chip development lifecycle.
• Deep technical expertise with multiple production tape-outs.
• Experience integrating complex ASIC IP blocks into SOC designs.

Responsibilities

• Own complete RTL design lifecycle from micro-architecture to production silicon.
• Drive full ASIC development lifecycle including timing analysis and verification.
• Collaborate with physical design to achieve timing closure.

Skills

Verilog RTL coding

Timing closure

Physical design awareness

Scripting languages (Python/Perl/Tcl)

Education

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Tools

PrimeTime

Tempus

Job description

Advanced Micro Devices, Inc. is seeking a Senior ASIC Design Engineer for their Silicon Design team in San Jose, CA. The role involves owning the complete RTL design lifecycle and working on complex IP design for next-generation embedded products.

Candidates should have deep expertise in Verilog RTL coding and experience with the entire ASIC development process, including timing closure and SOC integration. The role promotes mentoring junior engineers and leading projects to successful completion.