ASIC DFT Engineering Lead - Design-for-Test

Cisco Systems; Seattle (WA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems in Seattle, WA, is seeking an ASIC Implementation Technical Lead focused on Design-for-Test. You will partner with Front-end RTL and backend physical design to define DFT requirements early and guide the implementation flow through post-silicon validation.

You’ll work with ATE engineers on pattern translation and validation while shaping next-generation networking chips. Ideal candidates have 8+ years in EE/CE, strong ATPG/EDA tooling experience, and a track record in gate-level

Qualifications

• ATPG and EDA tool experience required.
• Hands-on experience with gate-level simulations and timing-based SDF.
• Post-silicon validation and debug experience needed.

Responsibilities

• Collaborate with Front-end RTL and Backend PD teams to define DFT requirements early.
• Lead DFT and quality processes across Implementation flow and post-silicon validation.
• Coordinate with ATE engineers on pattern translation and validation.
• Contribute to next-generation networking chip design and verification.

Skills

ATPG

Gate-level simulation

VCS debugging

Post-silicon validation

Scan insertion

JTAG p1500/p1687

Education

Bachelor’s degree in Electrical or Computer Engineering

Master’s degree in Electrical/Computer Engineering

PhD in Electrical/Computer Engineering

Tools

TestMax

Tetramax

Tessent

Job description

Cisco Systems in Seattle, WA, is seeking an ASIC Implementation Technical Lead focused on Design-for-Test. You will partner with Front-end RTL and backend physical design to define DFT requirements early and guide the implementation flow through post-silicon validation.

You’ll work with ATE engineers on pattern translation and validation while shaping next-generation networking chips. Ideal candidates have 8+ years in EE/CE, strong ATPG/EDA tooling experience, and a track record in gate-level