Senior ASIC DFT Implementation Lead

Cisco Systems; Austin (TX); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems is seeking an ASIC Implementation Technical Lead focused on Design-for-Test (DFT) to drive DFT requirements across the design cycle. You will partner with Front-end RTL and backend physical design teams to implement efficient test strategies and ensure quality through validation phases.

You will guide the DFT and quality processes, work with ATE engineers on pattern translation, and contribute to next-generation networking chips, leveraging your extensive post-silicon experience

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering with 8+ years of experience, or Master’s degree with 6+ years, or PhD with 3+ years.
• Experience with ATPG and EDA tools like TestMax or Tetramax or Tessent.
• Experience with gate-level simulation and timing-based simulations with SDF, debugging with VCS or similar.
• Post-silicon validation and debug experience.
• Experience with scan insertion.

Responsibilities

• Collaborate with Front-end RTL teams and backend physical design teams to drive DFT requirements early in the design cycle.
• Contribute to crafting next-generation networking chips and drive DFT and quality processes through implementation and post-silicon validation.
• Lead DFT and quality processes through the entire Implementation flow and post-silicon validation phases.
• Coordinate with ATE engineers on pattern translation and validation.

Skills

ATPG

EDA tools

Gate-level simulation

Post-silicon validation

Scan insertion

Verilog design

JTAG protocol

SSN

Scripting Tcl/Python/Perl

Timing constraints

Education

Bachelor’s in Electrical or Computer Engineering

Master’s in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

TestMax/Tetramax

Tessent

Job description

Cisco Systems is seeking an ASIC Implementation Technical Lead focused on Design-for-Test (DFT) to drive DFT requirements across the design cycle. You will partner with Front-end RTL and backend physical design teams to implement efficient test strategies and ensure quality through validation phases.

You will guide the DFT and quality processes, work with ATE engineers on pattern translation, and contribute to next-generation networking chips, leveraging your extensive post-silicon experience