Senior DFT Engineer — Post-Silicon Yield & Debug

Broadcom Inc.; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(k) with company matching

Employee Stock Purchase Program (ESPP)

Job summary

Broadcom Inc. is seeking a DFT Engineer for the Core Switching Group at our R&D center in San Jose, CA.

You will lead DFT ATPG/MBIST pattern development, debug, and drive yield improvements across wafer sort and final test, working with cross-functional teams and leveraging data analytics to build proactive yield models. The role demands deep CMOS physics knowledge, experience with Tessent, and strong scripting for automation; a Bachelor's degree with 8+ years (or a Master’s with 6+ years) is

Qualifications

• CMOS device physics and semiconductor manufacturing exposure.
• Experience with Scan/MBIST/bscan/IJTAG patterns using Tessent.
• Strong scripting and data-analysis abilities.

Responsibilities

• DFT Pattern post-silicon support: ATPG and MBIST patterns generation, bringup and debug
• Yield Enhancement: Monitor wafer sort and final test yield; drive improvements
• Root Cause Analysis: Scan diagnostic, MBIST and repair debug; correlate failures
• Failure Analysis: Support ATPG diag and guide physical failure analysis
• NPI & Silicon Bring-Up: Partner with Global Operation during early silicon evaluation
• Cross functional: Work closely with Product Engineers and Test Engineers
• Data Analytics & Automation: Use AI tools to build automated dashboards, wafer maps, and yield models

Skills

DFT Expertise

ATPG/MBIST

Pattern Bring-Up

Data Analytics

Scripting

Project Management

Education

Bachelor's Degree

Master's Degree

Tools

Mentor Tessent

Job description

Broadcom Inc. is seeking a DFT Engineer for the Core Switching Group at our R&D center in San Jose, CA.

You will lead DFT ATPG/MBIST pattern development, debug, and drive yield improvements across wafer sort and final test, working with cross-functional teams and leveraging data analytics to build proactive yield models. The role demands deep CMOS physics knowledge, experience with Tessent, and strong scripting for automation; a Bachelor's degree with 8+ years (or a Master’s with 6+ years) is