Senior ASIC DFT Architect & Debug Lead

Sapsol Technologies Inc; United States; Remote; USD 150,000 - 190,000; Full time

Job summary

Sapsol Technologies Inc. seeks a Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.

You will own DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation while guiding cross-functional debug teams to resolve silicon issues. The ideal candidate has deep DFT fundamentals, fault models, test coverage, and the ability to evaluate emerging methodologies to improve robustness, quality,

Qualifications

• Strong hands-on experience in ASIC DFT with end-to-end ownership.
• Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
• Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
• Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
• Experience with MBIST implementation and verification; SMS experience preferred.
• Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
• Strong understanding of PLLs, RTL design, synthesis flows, LEC, and physical design implementation.
• Proven post-silicon debug and silicon bring-up experience.
• Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
• Strong communication skills and the ability to work independently with minimal ramp-up.

Responsibilities

• Architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.
• Lead cross-functional debug efforts and drive resolution of critical silicon issues.
• Evaluate and adopt emerging DFT methodologies to improve robustness, quality, and yield.

Skills

DFT

ASIC design

ATPG

MBIST/LBIST

JTAG/boundary scan

post-silicon validation

scan architecture

EDa tools (Synopsys Cadence Mentors)

debugging

communication

Tools

Synopsys

Cadence

Siemens/Mentor

Job description

Sapsol Technologies Inc. seeks a Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.

You will own DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation while guiding cross-functional debug teams to resolve silicon issues. The ideal candidate has deep DFT fundamentals, fault models, test coverage, and the ability to evaluate emerging methodologies to improve robustness, quality,