Senior ASIC DFT Architect & Debug Leader

ITMC Systems, Inc; San Jose (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

ITMC Systems, Inc in San Jose, California is seeking a Lead ASIC DFT Engineer with 10+ years of experience. You will be responsible for designing, implementing, and verifying DFT solutions for complex ASIC and SoC designs. The ideal candidate possesses deep expertise in scan architecture, ATPG, and boundary scan. This role involves leading DFT integration and debug efforts, mentoring junior engineers, and using scripting languages like TCL and Python to improve workflows.

Qualifications

• 10+ years of hands-on experience in ASIC Design-for-Test (DFT).
• Strong hands-on experience in ASIC DFT with end-to-end ownership.
• Proven post-silicon debug and silicon bring-up experience.

Responsibilities

• Lead DFT architecture, implementation, verification, and sign-off for ASIC designs.
• Drive scan architecture and scan insertion workflows to achieve high coverage.
• Collaborate with design teams to resolve integration and implementation issues.

Skills

ASIC DFT expertise

DFT fundamentals

Scan architecture

ATPG

JTAG

TCL

Python scripting

Tools

Synopsys EDA tools

Cadence EDA tools

Siemens/Mentor EDA tools

Job description

ITMC Systems, Inc in San Jose, California is seeking a Lead ASIC DFT Engineer with 10+ years of experience. You will be responsible for designing, implementing, and verifying DFT solutions for complex ASIC and SoC designs. The ideal candidate possesses deep expertise in scan architecture, ATPG, and boundary scan. This role involves leading DFT integration and debug efforts, mentoring junior engineers, and using scripting languages like TCL and Python to improve workflows.