Senior ASIC DFT Engineer – Scan & ATPG

ALTEN; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

ALTEN is seeking candidates for an ASIC Design role in San Jose, California. The position involves implementation and verification of DFT/DFD techniques for low power designs. Candidates should have at least 6 years of experience in ASIC/DFT and a strong grasp of DFT concepts.

Responsibilities include optimizing SoC compression, scan insertion, debugging DRC issues, and ensuring compliance with ATPG coverage goals. A Bachelor's or Master's in Engineering is required, along with excellent problem-solving and communication skills.

Qualifications

• Minimum of 6 years experience in ASIC/DFT.
• In-depth knowledge of DFT concepts.
• Expertise in scripting languages such as Perl, shell.
• Ability to work in an international team, dynamic environment.

Responsibilities

• Analyze and propose best compression for given SoC/core/block.
• Own and deliver scan insertion, validate equivalence check.
• Debug/resolve DRC issues, ensure DFT DRCs are fixed.
• Analyze and meet ATPG coverage goals.

Skills

ASIC/DFT experience

DFT concepts knowledge

Scan insertion

ATPG and coverage analysis

Timing fixes expertise

Scripting (Perl, shell)

Simulating test vectors

Timing constraints definition

Problem solving skills

Communication and teamwork

Education

Bachelors or Masters in Engineering

Tools

Cadence Encounter Test

Synopsis TetraMax

Job description

ALTEN is seeking candidates for an ASIC Design role in San Jose, California. The position involves implementation and verification of DFT/DFD techniques for low power designs. Candidates should have at least 6 years of experience in ASIC/DFT and a strong grasp of DFT concepts.

Responsibilities include optimizing SoC compression, scan insertion, debugging DRC issues, and ensuring compliance with ATPG coverage goals. A Bachelor's or Master's in Engineering is required, along with excellent problem-solving and communication skills.