Engineer, Staff|6314 Engineer, Staff|6314

ALTEN; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

ALTEN is seeking candidates for an ASIC Design role in San Jose, California. The position involves implementation and verification of DFT/DFD techniques for low power designs. Candidates should have at least 6 years of experience in ASIC/DFT and a strong grasp of DFT concepts.

Responsibilities include optimizing SoC compression, scan insertion, debugging DRC issues, and ensuring compliance with ATPG coverage goals. A Bachelor's or Master's in Engineering is required, along with excellent problem-solving and communication skills.

Qualifications

• Minimum of 6 years experience in ASIC/DFT.
• In-depth knowledge of DFT concepts.
• Expertise in scripting languages such as Perl, shell.
• Ability to work in an international team, dynamic environment.

Responsibilities

• Analyze and propose best compression for given SoC/core/block.
• Own and deliver scan insertion, validate equivalence check.
• Debug/resolve DRC issues, ensure DFT DRCs are fixed.
• Analyze and meet ATPG coverage goals.

Skills

ASIC/DFT experience

DFT concepts knowledge

Scan insertion

ATPG and coverage analysis

Timing fixes expertise

Scripting (Perl, shell)

Simulating test vectors

Timing constraints definition

Problem solving skills

Communication and teamwork

Education

Bachelors or Masters in Engineering

Tools

Cadence Encounter Test

Synopsis TetraMax

Job description

Job Description: The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs. The candidate should have solid hands‑on experience with industry standard DFT techniques such as scan and MBIST.

Job Responsibilities

• Analyze and propose best compression for given SoC/core/block.
• Own and deliver scan insertion, validate equivalence check.
• Debug/resolve any DRC issues, identify solutions and work with front‑end team to ensure DFT DRCs are fixed.
• Analyze and meet ATPG coverage goals.
• Own STA constraints and work with STA team to resolve timing violations.
• Own IDDQ constraints generation and validation.
• Work independently in the team to solve problems, enabling the team to deliver on time with high quality.
• Responsible for deliverables of certain aspects of SoC DFT execution.
• Responsible for pattern verification and debug.

Qualifications

• Minimum of 6 years experience in ASIC/DFT.
• In depth knowledge of DFT concepts.
• Hands on experience in scan insertion, ATPG, coverage analysis, transition delay test coverage analysis.
• Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
• Expertise in scripting languages such as Perl, shell, etc.
• Experience in simulating test vectors.
• Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like Spyglass) and ATPG tool (e.g., TK, TetraMax).
• Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus.
• Ability to work in an international team, dynamic environment.
• Ability to learn and adapt to new tools and methodologies.
• Ability to do multi‑tasking and work on several high‑priority designs in parallel.
• Excellent problem solving skills.
• Excellent communication and teamwork skills and good English required.

Minimum Qualifications

Education: Bachelors or Masters in Engineering.

Work Experience: 6+ years in Hardware Engineering or related work experience.