DFT Design Engineer - ASIC/SoC & Scan Tech

1010 Analog Devices Inc.; Dallas (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Analog Devices, Inc. is seeking a qualified DFT/ASIC engineer to join our experienced team in Dallas. You will contribute to DFT specification, insertion, and verification across multiple product lines, and collaborate on high-coverage, low-power scan patterns.

Requires an MS in Electrical or Computer Engineering and at least 2 years of hands-on DFT experience with ATPG tools; familiarity with Tessent, IEEE 1149/JTAG, and scripting (Perl/Python/Tcl) is a plus. On-site position in Dallas.

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or similar.
• 2 years of directly related experience in ASIC/SoC DFT.
• Good understanding of DFT architecture and planning.
• Hands-on scan insertion and ATPG tool experience.
• Hands-on experience of DFT compression insertion, on-chip clock control insertion.
• Hands-on experience of gate-level simulation with zero delay and SDF.
• Good understanding of failure analysis.
• Scripting: Perl/Python/Tcl.
• Team-player: ability to forge and maintain relationships with peer-organizations.
• Strong written and verbal communication skills.

Responsibilities

• DFT specifications, architecture and implementation using state-of-the-art methodologies and tools.
• Support various product lines for DFT insertion.
• Support various product lines for High Coverage, Low Power, Low Test Time scan patterns.
• Pre/Post silicon verification & debug.
• Work independently as well as in team

Skills

DFT architecture

ATPG tooling

Scripting: Perl/Python/Tcl

Team collaboration

Communication skills

Problem solving

Education

Master's degree in Electrical Engineering or Computer Engineering

Tools

Tessent DFT tools

IEEE 1149/JTAG

LBIST/MBIST

Gate-level simulation (SDF)

Job description

Analog Devices, Inc. is seeking a qualified DFT/ASIC engineer to join our experienced team in Dallas. You will contribute to DFT specification, insertion, and verification across multiple product lines, and collaborate on high-coverage, low-power scan patterns.

Requires an MS in Electrical or Computer Engineering and at least 2 years of hands-on DFT experience with ATPG tools; familiarity with Tessent, IEEE 1149/JTAG, and scripting (Perl/Python/Tcl) is a plus. On-site position in Dallas.