Engineer, Senior|6288 Engineer, Senior|6288

ALTEN; San Diego (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

ALTEN is looking for an experienced candidate to join their Digital ASIC Design Team in San Diego, California. The role involves implementing and verifying DFT/DFD techniques to ensure successful chip design. A minimum of five years of experience in ASIC/DFT is required, along with a solid background in scan insertion and ATPG. Successful candidates will work within a dynamic international team, deliver solutions for complex chips, and communicate effectively. This position emphasizes both technical proficiency and collaborative skills.

Qualifications

• Minimum of 5-6 years experience in the area of ASIC/DFT.
• In depth knowledge of DFT concepts.
• Expertise in scripting languages such as Perl, shell, etc.

Responsibilities

• Contributing to DFT insertion and validation effort of complex chip.
• Analyze and propose best compression for given SoC/core/block.
• Debug/resolve DRC issues and ensure fixes with the front-end team.

Skills

DFT concepts

ASIC design

Scan insertion

ATPG

Coverage analysis

Perl scripting

Shell scripting

Problem solving

Teamwork

Adaptability to new tools

Education

Bachelor's or Master's in Engineering

Tools

Synopsis TetraMax

Cadence Encounter Test

RTL lint tool (like SpyGlass)

Job description

Job Description

The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs. The candidate should have solid hands‑on experience with industry standard DFT techniques such as scan and MBIST. Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations. The ideal candidate will have experience in both pre and post‑silicon in the DFT domain.

Job Function / Responsibilities

• Contributing to DFT insertion and validation effort of complex chip, core and/or blocks.
• Analyze, propose best compression that can be achieved for given SoC/core/block.
• Own and deliver scan insertion, validate equivalence check.
• Debug/resolve any DRC issues, identify solution and work with front‑end team to ensure DFT DRCs are fixed.
• Analyzing and meeting ATPG coverage goals.
• Owns STA constraints and work with STA team to resolve timing violations.
• Owns IDDQ constraints generation and validation.
• Working independently in the team to solve problems, enable his team to deliver on time with high quality.
• Responsible for deliverables of certain aspects of SoC DFT execution.
• Responsible for pattern verification and debug.

Skills / Experience

• Minimum of 5-6 years experience in the area of ASIC/DFT.
• In depth knowledge of DFT concepts.
• In depth knowledge and hands‑on experience in scan insertion, ATPG, coverage analysis, transition delay test coverage analysis.
• Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
• Expertise in scripting languages such as Perl, shell, etc.
• Experience in simulating test vectors.
• Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like SpyGlass) and ATPG tool like (TK, TetraMax).
• Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus.
• Ability to work in an international team, dynamic environment.
• Ability to learn and adapt to new tools and methodologies.
• Ability to do multi‑tasking & work on several high priority designs in parallel.
• Excellent problem solving skills.

Excellent communication and teamwork skills and good English is required.

Minimum Qualifications

• Education: Bachelor/Master - Engineering.
• Work Experiences: 6+ years Hardware Engineering experience or related work experience.