DFT ASIC Engineer — RTL/Scan, ATPG & Verification

Spacex; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

SpaceX is seeking an ASIC/SOC DFT Engineer (Silicon Engineering) to develop next-generation ASICs for space and ground infrastructure. You will work with cross-disciplinary teams to design, implement, and verify scan insertion and DFT features that enable reliable post-silicon testing.

The role requires 1+ year of ASIC experience, knowledge of RTL/DFT flows, and scripting skills. ITAR-restricted positions; strong collaboration across design and manufacturing is essential.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional experience working with ASICs.
• Experience in scan insertion or DFT setup.
• Understanding of ASIC design flow and physical design is a plus.

Responsibilities

• Evaluate design readiness for scan insertion through RTL and physical design DRC tools.
• Integrate and verify DFT fabrics and IP within Subsystems.
• Run ATPG analysis to ensure quality scan chain construction and coverage.
• Collaborate with circuit physical design, ATPG, and manufacturing teams to achieve high-quality scan coverage.

Skills

Scan insertion

DFT concepts

Scripting

Verilog/SystemVerilog

ASIC design knowledge

Education

Bachelor’s degree in electrical engineering / computer engineering / computer science

Tools

Verilog/SystemVerilog

UPF (Unified Power Format)

Job description

SpaceX is seeking an ASIC/SOC DFT Engineer (Silicon Engineering) to develop next-generation ASICs for space and ground infrastructure. You will work with cross-disciplinary teams to design, implement, and verify scan insertion and DFT features that enable reliable post-silicon testing.

The role requires 1+ year of ASIC experience, knowledge of RTL/DFT flows, and scripting skills. ITAR-restricted positions; strong collaboration across design and manufacturing is essential.