DFT ASIC Engineer — RTL/Scan & ATPG

SPACE EXPLORATION TECHNOLOGIES CORP; Palo Alto (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Health benefits

Paid vacation

Job summary

SpaceX is seeking an ASIC/SOC DFT Engineer (Silicon Engineering) to develop cutting-edge ASICs for Starlink. You will work with cross-functional teams to design, verify, and implement scan insertion, DFT fabrics, and ATPG for high-reliability space systems.

The role requires a Bachelor’s in EE/CE/CS and 1+ years in ASICs, with experience in Verilog/SystemVerilog, UPF, and design-for-test workflows. Expect a highly dynamic, collaborative environment with long-term growth.

Qualifications

• Experience with ASIC design flow and verification.
• 1+ years of professional ASIC experience.
• Experience with scan insertion or DFT setup.

Responsibilities

• Evaluate design readiness for scan insertion using RTL and DRC tools.
• Integrate and verify DFT fabrics and IP within subsystems.
• Run and optimize scan insertion via synthesis tools.
• Perform ATPG analysis to ensure scan coverage.
• Run gate-level simulations including non-timing and SDF annotations.
• Collaborate with circuit design, ATPG, and manufacturing teams to improve silicon scan coverage.

Skills

Scan insertion

DFT

Verilog/SystemVerilog

ASIC experience

RTL verification

Synthesis tools

Education

Bachelor's degree in electrical engineering, computer engineering or computer science

Tools

UPF

ATPG

DRC tools

Job description

SpaceX is seeking an ASIC/SOC DFT Engineer (Silicon Engineering) to develop cutting-edge ASICs for Starlink. You will work with cross-functional teams to design, verify, and implement scan insertion, DFT fabrics, and ATPG for high-reliability space systems.

The role requires a Bachelor’s in EE/CE/CS and 1+ years in ASICs, with experience in Verilog/SystemVerilog, UPF, and design-for-test workflows. Expect a highly dynamic, collaborative environment with long-term growth.