ASIC & SOC DFT Engineer — RTL/ATPG Specialist

InvestedintheMission; Palo Alto (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Medical, vision, and dental coverage

Paid vacation and holidays

Disability and life insurance

Job summary

SpaceX is seeking an ASIC/DFT Engineer (Silicon Engineering) to develop next-generation ASICs for space and ground infrastructures. You will work with cross-disciplinary teams to implement design-for-test and scan insertion strategies, ensuring high-quality scan coverage and robust verification.

The role requires a bachelor's in a relevant field, 1+ years of ASIC experience, and strong scripting and Verilog/SystemVerilog skills. ITAR compliance and a dynamic work environment are part of the job.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional experience working with ASICs.
• Experience in scan insertion or DFT setup.

Responsibilities

• Evaluate design readiness for scan insertion through RTL and physical design DRC tools.
• Integrate and verify Design for Test (DFT) fabrics and IP within Subsystems.
• Run and refine scan insertion through synthesis tools for maximum coverage.
• Perform ATPG analysis to ensure scan chain quality and coverage goals.
• Run and debug non-timing and SDF annotated gate-level simulations.
• Create ATPG content for post-silicon testing and validate with gate-level sim.
• Collaborate with circuit physical design, ATPG and manufacturing teams for high-quality scan coverage.

Skills

DFT concepts

Scan insertion experience

Python/Perl scripting

Verilog/SystemVerilog familiarity

UPF familiarity

Synthesis tools

ATP G/ATPG

Team collaboration

Education

Bachelor's degree in electrical/computer engineering or computer science

Tools

Verilog/SystemVerilog

UPF

DFT tools

Synthesis tools

Job description

SpaceX is seeking an ASIC/DFT Engineer (Silicon Engineering) to develop next-generation ASICs for space and ground infrastructures. You will work with cross-disciplinary teams to implement design-for-test and scan insertion strategies, ensuring high-quality scan coverage and robust verification.

The role requires a bachelor's in a relevant field, 1+ years of ASIC experience, and strong scripting and Verilog/SystemVerilog skills. ITAR compliance and a dynamic work environment are part of the job.