DFT Engineer

Anysilicon; San Jose, Northern (CA, KY); Hybrid; USD 120,000 - 150,000; Full time

Job summary

Broadcom's San Jose Development Center seeks a DFT Engineer to drive DFT feature specification, vector generation, and validation across ASICs. You will implement Scan, MBIST, TAP, LBIST, and SerDes DFT techniques and support silicon bring-up activities.

The role requires strong Verilog coding, testbench development, and memory BIST experience, with collaboration across Physical Design and STA teams. On-site in San Jose, CA.

Qualifications

• Bachelor's degree in Electrical/Electronic/Computer Engineering with 2+ years of relevant industry experience, or a Master's degree in the same fields.

Responsibilities

• Understand Broadcom and customer DFT feature requirements and define appropriate DFT specifications for ASICs.
• Implement DFT techniques including Scan, MBIST, TAP, LBIST, IO, SerDes, and other I/P DFT integrations.
• Generate, verify, and debug test vectors before tape release.
• Validate and debug test vectors on ATE during the silicon bring-up phase.
• Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
• Automate DFT and test vector generation flows.

Skills

DFT flows

Verilog

Testbench generation

Simulation

Memory BIST insertion

Test-STA

IEEE 1687 / IJTAG / ICL / PDL

Cross-discipline collaboration

Analog & digital design knowledge

Silicon processing & physical concepts

Education

Bachelor's degree in Electrical/Electronic/Computer Engineering

Master's degree in Electrical/Electronic/Computer Engineering

Tools

Verilog

Testbench

Simulation

Job description

Broadcom's ASIC Product Division is seeking a DFT Engineer for its San Jose, California Development Center. The role involves working on various phases of SoC DFT activities, including test insertion, verification, pattern generation, and yield improvement, while collaborating with the Physical Design & STA team. Candidates should be proficient in coding with languages such as TCL, PERL, RUBY, PYTHON, or C++.

Responsibilities:

• Understand Broadcom and customer DFT feature requirements and define appropriate DFT specifications for ASICs.
• Implement DFT techniques including Scan, MBIST, TAP, LBIST, IO, SerDes, and other I/P DFT integrations.
• Generate, verify, and debug test vectors before tape release.
• Validate and debug test vectors on ATE during the silicon bring-up phase.
• Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
• Automate DFT and test vector generation flows.

Qualifications:

• Bachelor's degree in Electrical/Electronic/Computer Engineering with 2+ years of relevant industry experience, or a Master's degree in the same fields.

Skills:

• Exposure to DFT flows.
• Experience in Verilog coding, testbench generation, and simulation.
• Memory BIST insertion and verification experience on embedded memory types (SRAM, CAM, eDRAM, ROM).
• Basic knowledge of Test-STA and constraints.
• Strong background in IEE1687, IJTAG, ICL, and PDL.
• Ability to work in a multi-disciplined, cross-department environment.
• Solid knowledge of analog and digital circuit design and device physics fundamentals.
• Good understanding of silicon processing, logical and physical synthesis, and transistor reliability principles.
• Excellent problem-solving, debugging, root cause analysis, and communication skills.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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