DFT Engineer

Quest Global; Santa Clara (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Quest Global in California is seeking an experienced Design for Test (DFT) Engineer to contribute to the development of complex SoC/ASIC designs. You will lead DFT planning and integration, define testing methodologies, and pursue continuous improvements of DFT flows across chip-level and block-level implementations to ensure robust manufacturing outcomes.

The role emphasizes hands-on work with Tessent tool flows, ATPG generation, ATE interface integration, and silicon failure analysis.

Qualifications

• Bachelor’s degree with 8+ years of experience or Master’s degree with 9+ years of experience.
• Extensive hands‑on experience in DFT for ASIC/SoC designs.
• Strong expertise in chip‑level DFT planning and integration.
• Deep knowledge of LBIST (at-speed scan), ATPG, MBIST, and JTAG.
• Experience with test time reduction methodologies.
• Solid understanding of low power DFT and fault modeling (stuck-at, transition, path delay, IDDQ, etc.).
• Experience with silicon failure analysis and debugging.
• Strong knowledge of static timing analysis (STA).
• Experience with DFT simulations including timing considerations.
• Familiarity with ASIC/SoC design flows, including low power and multi‑power domain designs.
• Experience working with Mentor DFT tools or similar EDA tools.

Responsibilities

• Develop and implement top-level and block-level DFT plans and integrations.
• Utilize Tessent tool flow extensively across DFT processes.
• Perform ATPG generation and support ATE interface integration.
• Support ATE bring-up and conduct silicon failure analysis and debugging.
• Analyze and reduce test time while maintaining high quality standards.
• Execute synthesis, STA, and simulation for DFT modes.
• Perform formal verification and ensure design correctness.
• Implement and manage multi-power domain DFT strategies.
• Troubleshoot complex DFT issues and drive continuous DFT flow improvements.

Skills

DFT planning

integration

ATPG

LBIST

JTAG

low power DFT

synthesis/STA

debugging silicon

test time reduction

DFT simulations

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering or related field

Tools

Mentor DFT tools

EDA tool flows

Job description

We are seeking a highly experienced Design for Test (DFT) Engineer to contribute to the development of complex SoC/ASIC designs. This role will focus on DFT planning, integration, testing methodologies, and continuous improvement of DFT flows across chip-level and block level implementations.

Key Responsibilities:

• Develop and implement top-level and block-level DFT plans and integrations
• Utilize Tessent tool flow extensively across DFT processes
• Perform ATPG generation and support ATE interface integration
• Support ATE bring-up and conduct silicon failure analysis and debugging
• Analyze and reduce test time while maintaining high quality standards
• Execute synthesis, STA, and simulation for DFT modes
• Perform formal verification and ensure design correctness
• Implement and manage multi-power domain DFT strategies
• Troubleshoot complex DFT issues and drive continuous DFT flow improvements

Qualifications:

• Bachelor’s degree with 8+ years of experience OR Master’s degree with 9+ years of experience
• Extensive hands‑on experience in DFT for ASIC/SoC designs
• Strong expertise in chip‑level DFT planning and integration
• Deep knowledge of LBIST (at-speed scan), ATPG, MBIST, and JTAG
• Experience with test time reduction methodologies
• Solid understanding of low power DFT and fault modeling (stuck-at, transition, path delay, IDDQ, etc.)
• Experience with silicon failure analysis and debugging
• Strong knowledge of static timing analysis (STA)
• Experience with DFT simulations including timing considerations
• Familiarity with ASIC/SoC design flows, including low power and multi‑power domain designs
• Experience working with Mentor DFT tools or similar EDA tools