Senior ASIC DFT Verification Engineer – SoC Expert

Meta; Austin (TX); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Equity participation

Bonus program

Benefits package

Job summary

Meta is hiring an ASIC Design Verification Engineer specializing in Design for Testability (DFT) within the Infrastructure Silicon team in Austin, TX. You will drive DFT verification closure across IP, sub-system, and SoC levels, ensuring scan, BIST, JTAG, and related structures are robust and verifiable.

You will collaborate with DFT Architects, Emulation, and Post-Silicon Validation teams to validate pre- and post-silicon results, develop scalable verification environments, and automate flows

Qualifications

• Requires 8+ years in ASIC design verification with SystemVerilog/UVM
• Deep experience with DFT verification: scan insertion, ATPG, BIST, JTAG
• Proficiency in scripting (Python/Tcl/Perl) for flow automation
• IP/SoC-level verification closure including test planning and coverage analysis
• Familiarity with formal verification for DFT control logic

Responsibilities

• Define DFT verification plans for scan, ATPG, BIST, JTAG across IP/sub-system/SoC
• Develop UVM- and C/C++-based testbenches to verify DFT logic
• Drive verification closure using functional, code, and DFT coverage metrics
• Review DFT insertion methods with architects and designers
• Debug root-cause DFT issues pre-silicon
• Develop and validate ATPG pattern generation flows
• Apply formal verification to DFT control logic and scan paths
• Collaborate with emulation and post-silicon teams for bring-up
• Build verification infrastructure and automated flows
• Contribute to ongoing DFT methodology improvements

Skills

UVM-based testbenches

SystemVerilog

DFT verification

Python scripting

Verification planning

Education

Bachelor's degree in CS/CE or related field

Tools

EDA tools for DFT insertion/ATPG

Job description

Meta is hiring an ASIC Design Verification Engineer specializing in Design for Testability (DFT) within the Infrastructure Silicon team in Austin, TX. You will drive DFT verification closure across IP, sub-system, and SoC levels, ensuring scan, BIST, JTAG, and related structures are robust and verifiable.

You will collaborate with DFT Architects, Emulation, and Post-Silicon Validation teams to validate pre- and post-silicon results, develop scalable verification environments, and automate flows