ASIC Design and Integration Engineer

Apple Inc.; Beaverton (OR); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading technology company in Beaverton is seeking a highly skilled ASIC Design Engineer to develop custom SoCs. Responsibilities include design, implementation, verification of ASICs using SystemVerilog, and collaboration with hardware/software teams. The ideal candidate has a Bachelor's degree plus 3 years of industry experience, proficiency in ASIC design tools, and excellent problem-solving skills. Apple promotes inclusion and diversity in its employment practices.

Qualifications

• Minimum of BS + 3 years relevant industry experience.
• Experience in ASIC design, including RTL design and verification.
• Hands on experience in front-end chip development process.

Responsibilities

• Design, implementation, and verification of complex ASICs.
• Engage with verification teams for robust design validation.
• Collaborate to integrate digital designs into complex SoCs.
• Conduct timing analysis and power optimization.
• Create detailed micro-architecture and design documentation.

Skills

Proficiency in SystemVerilog

RTL design

Synthesis

Timing analysis

Problem-solving skills

Attention to detail

Collaboration skills

Experience with high-speed I/O design

Knowledge of low-power design techniques

Education

Bachelor's or Master's degree in Electrical Engineering

3 years relevant industry experience

Tools

ASIC design tools

Job description

Apple’s Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance and efficiency of Apple’s products. You will work on cutting‑edge technologies and collaborate with cross‑functional teams to deliver groundbreaking solutions.

Description

Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis.

Verification: Engage with simulation‑based and formal verification teams to ensure robust design validation.

Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs.

Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals.

Documentation and Reporting: Create detailed micro‑architecture and design documentation.

Minimum Qualifications

• Minimum of BS + 3 years relevant industry experience

Preferred Qualifications

• Educational Background: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 3+ years of proven experience in ASIC design, including RTL design and verification. Hands‑on experience with ASIC design tools and methodologies is essential.
• Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
• Problem‑Solving: Strong analytical and problem‑solving skills.
• Collaboration: Excellent communication and teamwork skills, work effectively in cross‑functional teams.
• Attention to Detail: Meticulous attention to detail and a commitment to delivering high‑quality designs.
• Experience with high‑speed I/O design and protocols. Knowledge of PCIe is a plus.
• Familiarity with custom ASIC design and FPGA prototyping.
• Hands on experience in all aspects of front‑end chip development process (e.g., CDC/RDC, LINT, LEC, etc.).
• Knowledge of low‑power design techniques and power optimization strategies.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.