ASIC Design Engineer – Pixel IP DMA

Anysilicon; Sunnyvale, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Apple is seeking a Pixel IP DMA Design Engineer in Sunnyvale to design high-performance, low-power DMA engines for the Pixel IP Engine. You will collaborate with architecture, design and verification teams to deliver robust RTL implementations and optimize power and area.

The role emphasizes DMA engine development for ML/data storage and image processing, with strong focus on arbitration, address translation, caching, and on-chip interconnects.

Qualifications

• Bachelor's Degree in a relevant field with 10 years of experience in multimedia IP/SoC front-end ASIC RTL design.
• Experience in designing dedicated DMA engines, particularly for ML, data storage, memory controllers, networking and image processing.
• Strong understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis.

Responsibilities

• Design and develop high-performance, low-power DMA engines for data movement between memory systems and the Pixel IP Engine.
• Explore solutions to improve performance while minimizing power consumption and area.
• Detail specifications and create RTL designs for DMA engines.
• Collaborate with design verification and formal verification teams to ensure functionality and performance of designs.

Skills

DMA design

RTL design

AXI protocol

Synthesis

Power analysis

Team collaboration

Education

Bachelor's degree in EE/CS/related field

Tools

AMBA AXI

Linting

Job description

Join Apple's Hardware Technologies group as a Pixel IP DMA Design Engineer, where you'll design high-performance, power-efficient system-on-chips (SoCs) that enhance the functionality of Apple products. This role focuses on pixel processing and involves collaboration across teams to deliver innovative solutions that impact millions of customers.

Responsibilities:

• Design and develop high-performance, low-power DMA engines for data movement between memory systems and the Pixel IP Engine.
• Explore solutions to improve performance while minimizing power consumption and area.
• Detail specifications and create RTL designs for DMA engines.
• Collaborate with design verification and formal verification teams to ensure functionality and performance of designs.

Qualifications:

• Bachelor's Degree in a relevant field with 10 years of experience in multimedia IP/SoC front-end ASIC RTL design.
• Experience in designing dedicated DMA engines, particularly for machine learning, data storage, memory controllers, networking, and image processing.
• Strong understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis.

Skills:

• Excellent written and verbal communication skills for effective collaboration.
• Proficiency in working with architecture, design, and verification teams to specify, design, and debug complex systems.
• Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
• Experience in front-end implementation tasks including synthesis, area and power analysis, linting, and logic equivalence checks.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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