Senior ASIC Design Engineer: RTL, IP & SoC Integration

Apple Inc.; Beaverton (OR); On-site; USD 150,000 - 210,000; Full time

Job summary

Apple seeks an experienced ASIC Design Engineer to join our hardware teams in Beaverton, OR. You will contribute to SOC design, IP integration, and front-end verification through the full development cycle.

You will write microarchitectures and specifications, debug complex logic, and collaborate across hardware and software groups to deliver high-quality Apple silicon products in a fast-paced environment.

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Verilog RTL Logic Design experience.

Responsibilities

• Write microarchitecture and/or design specifications.
• Design, implement, and debug complex logic designs.
• Integrate complex IPs into the SOC.
• Support all front end integration activities like Lint, CDC, Synthesis, and ECO.
• Work with SOC Design teams and other specialists to ensure high quality.

Skills

Verilog RTL Logic Design

Education

BS in Electrical Engineering or related field

Job description

Apple seeks an experienced ASIC Design Engineer to join our hardware teams in Beaverton, OR. You will contribute to SOC design, IP integration, and front-end verification through the full development cycle.

You will write microarchitectures and specifications, debug complex logic, and collaborate across hardware and software groups to deliver high-quality Apple silicon products in a fast-paced environment.