Senior VLSI/ASIC Design Architect (Hybrid)

Hewlett Packard Enterprise

Sunnyvale (CA)

Hybrid

USD 174,000 - 353,000

Full time

4 days ago
Be an early applicant

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Job summary

Hewlett Packard Enterprise in Sunnyvale, California, seeks a Principle VLSI/ASIC Design Engineer to drive architecture, RTL design, and integration of complex SoC solutions. The role is hybrid, requiring on-site collaboration two days per week with strong leadership across teams.

You will mentor engineers, influence architectural direction, and deliver production-ready designs for networking, compute, and other high-performance applications in a dynamic, global organization.

Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be considered.
  • Typically, 9+ years of experience in ASIC, VLSI, SoC, or related hardware design.
  • Experience designing complex RTL blocks for networking, compute, communications, storage, or other advanced SoC applications.
  • Experience leading architecture and design exploration through RTL implementation and product integration.

Responsibilities

  • Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications.
  • Define architectural approaches, microarchitectures, design methodologies, and implementation plans aligned with product requirements and technology roadmaps.
  • Design, develop, and modify complex RTL blocks using industry-standard HDL and design practices.
  • Drive RTL implementation from architectural definition through synthesis, physical implementation support, timing closure, and production readiness.
  • Analyze design tradeoffs involving performance, power, area, scalability, reliability, and time to market.
  • Mentor engineers and promote design innovation, engineering excellence, and knowledge sharing.

Skills

ASIC/VLSI design
Verilog/SystemVerilog
RTL design
design flows
analytical skills
design methodologies
innovation
communication skills
influence decisions
collaboration
mentoring

Education

Bachelor’s or Master in Electrical/Computer Engineering

Job description

Hewlett Packard Enterprise in Sunnyvale, California, seeks a Principle VLSI/ASIC Design Engineer to drive architecture, RTL design, and integration of complex SoC solutions. The role is hybrid, requiring on-site collaboration two days per week with strong leadership across teams.

You will mentor engineers, influence architectural direction, and deliver production-ready designs for networking, compute, and other high-performance applications in a dynamic, global organization.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior VLSI Architect & Technologist (Hybrid)
Senior VLSI Architect & Technologist (Hybrid)

Tealhq • Sunnyvale (CA)

Hybrid
USD 220,000 - 320,000
Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion
Hybrid Senior VLSI Architect & Tech Leader
Hybrid Senior VLSI Architect & Tech Leader

Hewlett Packard Enterprise • Sunnyvale (CA)

Hybrid
USD 174,000 - 353,000
Hybrid VLSI Design Lead
Hybrid VLSI Design Lead

Hewlett Packard Enterprise • Sunnyvale (CA)

Hybrid
USD 150,000 - 210,000
Senior VLSI ASIC Logic Design Engineer - Hybrid
Senior VLSI ASIC Logic Design Engineer - Hybrid

Hewlett Packard Enterprise • Fort Collins (CO)

Hybrid
USD 147,000 - 279,000
Principal ASIC Design Engineer | Hybrid, Equity & Bonus
Principal ASIC Design Engineer | Hybrid, Equity & Bonus

HP Enterprise • Sunnyvale (CA)

Hybrid
USD 180,000 - 290,000
Annual equity awards
Hybrid work model
Annual bonus
Senior VLSI Technologist & Architectural Leader (Hybrid)
Senior VLSI Technologist & Architectural Leader (Hybrid)

Hewlett Packard Enterprise • Sunnyvale (CA)

Hybrid
USD 183,000 - 390,000
Hybrid work model
Hybrid Senior ASIC Verification Engineer
Hybrid Senior ASIC Verification Engineer

Hewlett Packard Enterprise Company • Sunnyvale (CA)

Hybrid
USD 159,000 - 321,000
Senior VLSI ASIC Design Lead: Architecture to Validation
Senior VLSI ASIC Design Lead: Architecture to Validation

Hewlett Packard Enterprise • United States

On-site
USD 140,000 - 321,000
Senior Principal ASIC Design Lead – High-Perf Networking
Senior Principal ASIC Design Lead – High-Perf Networking

HITEC • Roseville (CA)

Hybrid
USD 174,000 - 353,000
Senior ASIC Verification Architect — Hybrid (2 days in office)
Senior ASIC Verification Architect — Hybrid (2 days in office)

HITEC • Chippewa Falls (WI)

Hybrid
USD 140,000 - 321,000
Hybrid work model
Inclusive culture