Senior ASIC Design Lead: AI/LLM Networking Processor

Fortinet; Sunnyvale (CA); Presencial; USD 192 000 - 270 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Medical insurance

Dental insurance

Vision insurance

Life & Disability Insurance

401(k)

11 paid holidays

Vacation time

Sick time

Comprehensive leave program

Resumo da oferta

Fortinet in Sunnyvale seeks an experienced ASIC Designer to join its R&D team and accelerate FortiASIC technology for high-performance security systems.

You will work from specification through RTL implementation, lead IP integration, and verify chip-level RTL design. The role requires deep knowledge of SystemVerilog/UVM, AI/LLM accelerators, and collaboration with cross-functional teams in a fast-paced environment.

Qualificações

• Proven experience in high-performance ASIC/processor design.
• Strong background in SystemVerilog and UVM verification.
• Hands-on Verilog/SystemVerilog coding, synthesis, and verification.
• Experience with AI/LLM accelerator or NPU design.

Responsabilidades

• Micro-Architecture: define and refine micro-architecture of FortiASICs.
• Verification & Coverage: review test plans, perform coverage analysis, run full-chip simulations.
• RTL & Design Implementation: implement using SystemVerilog/Verilog, conduct lint/CDC reviews, synthesis, timing analysis, IP integration.
• Physical Design & PPA: verify constraints, optimize placement and routing, close timing, optimize PPA.
• FPGA Prototyping: emulate and prototype designs on FPGAs for full validation.
• Bring-Up & Support: participate in system/board bring-up and post-silicon debugging.
• Execution & Collaboration: self-starter with strong cross-functional teamwork.

Conhecimentos

Verilog/SystemVerilog HDL

UVM verification

AI/LLM accelerator

NPU design

Formação académica

B.S./M.S. in EE/CE/CS

Descrição da oferta de emprego

Fortinet in Sunnyvale seeks an experienced ASIC Designer to join its R&D team and accelerate FortiASIC technology for high-performance security systems.

You will work from specification through RTL implementation, lead IP integration, and verify chip-level RTL design. The role requires deep knowledge of SystemVerilog/UVM, AI/LLM accelerators, and collaboration with cross-functional teams in a fast-paced environment.