Senior ASIC Design Architect—AI-Driven Verification

Palo Alto Networks

California

Presencial

USD 156.000 - 253.000

Jornada completa

14 días+

Una candidatura completa en un minuto

Currículum y carta de presentación personalizados, listos para enviar.

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Descripción de la vacante

Palo Alto Networks is seeking an experienced ASIC design lead for our ASIC team. You will own module design from specification through silicon bring-up, collaborating with verification and physical-design to meet aggressive performance, power, and schedule goals.

The role requires 10+ years of front-end ASIC design ownership, expert SystemVerilog RTL skills, and strong scripting abilities. Networking or cybersecurity domain knowledge is a plus.

Formación

  • 10+ years of front-end ASIC design ownership and shipping 2+ chips.
  • Expert SystemVerilog RTL skills and IP integration experience.
  • Experience with high-speed interfaces such as PCIe, Ethernet, or DDR.
  • Strong scripting skills (Python, C/C++, Perl, bash).
  • Proven leadership and collaboration in cross-functional teams.

Responsabilidades

  • Write design and micro-architecture specifications.
  • Design SystemVerilog RTL meeting area, performance, and power targets.
  • Verify blocks with simulation, emulation, formal methods, and silicon bring-up.
  • Collaborate with verification to debug scenarios, close coverage, and add debug features.
  • Partner with physical-design to review synthesis/timing and floor-planning.
  • Innovate: pilot AI-driven design or verification flows to cut schedule risk.

Conocimientos

SystemVerilog RTL
Python
C/C++
High-speed interfaces

Educación

BS in EE/CE/CS
MS EE or equivalent military experience

Herramientas

PCIe IP blocks
Ethernet IP blocks
DDR IP blocks

Descripción del empleo

Palo Alto Networks is seeking an experienced ASIC design lead for our ASIC team. You will own module design from specification through silicon bring-up, collaborating with verification and physical-design to meet aggressive performance, power, and schedule goals.

The role requires 10+ years of front-end ASIC design ownership, expert SystemVerilog RTL skills, and strong scripting abilities. Networking or cybersecurity domain knowledge is a plus.

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