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Palo Alto Networks is seeking an experienced ASIC design lead for our ASIC team. You will own module design from specification through silicon bring-up, collaborating with verification and physical-design to meet aggressive performance, power, and schedule goals.
The role requires 10+ years of front-end ASIC design ownership, expert SystemVerilog RTL skills, and strong scripting abilities. Networking or cybersecurity domain knowledge is a plus.
Palo Alto Networks is seeking an experienced ASIC design lead for our ASIC team. You will own module design from specification through silicon bring-up, collaborating with verification and physical-design to meet aggressive performance, power, and schedule goals.
The role requires 10+ years of front-end ASIC design ownership, expert SystemVerilog RTL skills, and strong scripting abilities. Networking or cybersecurity domain knowledge is a plus.