Senior ASIC Design Engineer — AI Inference Hardware

Tensordyne; Sunnyvale (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Meals

Snacks & drinks

Unlimited PTO

Flexible work hours

Job summary

Tensordyne, a Sunnyvale-based AI system solutions company, seeks a Sr ASIC engineer to lead microarchitecture and RTL implementation for high‑performance AI accelerators.

You will collaborate with CPU/IP teams, drive timing closure, power optimization, and silicon validation, while integrating third‑party IP to enable scalable, low‑power inference workloads in a dynamic startup environment.

Qualifications

• 10+ years of ASIC design with RTL in multi-million gate devices.
• Experience in CPU/IP integration into SoC.
• Knowledge of ARM/RISC-V/MIPS architectures, memory hierarchy, cache coherency.
• Familiarity with AMBA/APB/AXI protocols and peripheral interfaces.
• End-to-end ASIC development with front-end tools and methodologies.
• Familiarity with low power design and UPF flow.
• Startup environment willingness and self-motivation.
• BS (MS preferred) in Electrical or Computer Engineering.

Responsibilities

• Author micro-architecture specs and participate in reviews.
• Architect and implement complex RTL designs.
• Scope third party IP requirements and solicit vendors.
• Integrate CPU and other IP into the CPU sub-system.
• Collaborate with physical design to resolve timing and power issues.
• Analyze coverage and provide feedback for verification.
• Perform post-silicon validation tests and assist software bring-up.

Skills

RTL design

Verilog/SystemVerilog

CPU/IP integration

ARM/RISC-V/MIPS architectures

AMBA/AXI/APB protocols

Low power design / UPF

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

UPF flow

Job description

Tensordyne, a Sunnyvale-based AI system solutions company, seeks a Sr ASIC engineer to lead microarchitecture and RTL implementation for high‑performance AI accelerators.

You will collaborate with CPU/IP teams, drive timing closure, power optimization, and silicon validation, while integrating third‑party IP to enable scalable, low‑power inference workloads in a dynamic startup environment.