Principal ASIC Designer – AI/LLM Accelerator, Equity Eligible

Perception Point; Sunnyvale (CA); Presencial; USD 192 000 - 235 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Medical Insurance

Dental Insurance

Vision Insurance

401(k)

Paid Holidays

Leave Program

Equity Program

Resumo da oferta

Fortinet in Sunnyvale, CA is seeking an experienced ASIC Designer to join our R&D team to architect and deliver the next-generation FortiASIC technology for high-performance network security systems.

The role covers RTL implementation, IP integration, and full chip-level verification, from specification through bring-up. Candidates should have 8+ years in high-performance ASIC/FPGA design, strong SystemVerilog/UVM skills, and a track record of delivering complex silicon.

Qualificações

• 8+ years of experience in high-performance networking or processor design.
• Proven track record of taking complex ASIC/FPGA designs from concept to mass production.
• Hands-on Verilog / SystemVerilog HDL coding, synthesis, and design verification.
• Experience across the full ASIC development lifecycle—from specification through bring-up.
• Strong SystemVerilog and UVM verification methodologies.
• Background in AI/LLM accelerator or NPU design.

Responsabilidades

• Micro-Architecture: Define and refine the micro-architecture of FortiASICs with the architecture team.
• Verification & Coverage: Review test plans, perform coverage analysis, and run full-chip simulations.
• RTL & Design Implementation: Implement designs using SystemVerilog/Verilog HDL, conduct synthesis and IP integration.
• Physical Design & PPA: Verify constraints, optimize placement and routing, close timing, optimize PPA.
• FPGA Prototyping: Emulate and prototype designs using FPGAs for debugging and validation.
• Bring-Up & Support: Participate in system/board bring-up, post-silicon debugging, and ongoing support.
• Execution & Collaboration: Self-starter who manages time with cross-functional teamwork.

Conhecimentos

Verilog / SystemVerilog HDL

UVM verification

AI/LLM accelerator design

High-performance ASIC/processor design

Synthesis & timing analysis

Formação académica

B.S. or M.S. in EE/CE/CS

Ferramentas

Altera (Intel) / AMD Xilinx FPGA architectures

EDA tools

IP portfolios

Descrição da oferta de emprego

Fortinet in Sunnyvale, CA is seeking an experienced ASIC Designer to join our R&D team to architect and deliver the next-generation FortiASIC technology for high-performance network security systems.

The role covers RTL implementation, IP integration, and full chip-level verification, from specification through bring-up. Candidates should have 8+ years in high-performance ASIC/FPGA design, strong SystemVerilog/UVM skills, and a track record of delivering complex silicon.